openpic: Unfold write_IRQreg
The helper function write_IRQreg was always called with a specific argument on the type of register to access. Inside the function we were simply doing a switch on that constant argument again. It's a lot easier to just unfold this into two separate functions and call each individually. Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf
parent
8d3a8c1e77
commit
11de8b7166
79
hw/openpic.c
79
hw/openpic.c
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@ -482,30 +482,25 @@ static inline uint32_t read_IRQreg_ipvp(openpic_t *opp, int n_IRQ)
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return opp->src[n_IRQ].ipvp;
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}
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static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
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uint32_t reg, uint32_t val)
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static inline void write_IRQreg_ide(openpic_t *opp, int n_IRQ, uint32_t val)
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{
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uint32_t tmp;
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switch (reg) {
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case IRQ_IPVP:
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/* NOTE: not fully accurate for special IRQs, but simple and
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sufficient */
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/* ACTIVITY bit is read-only */
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opp->src[n_IRQ].ipvp =
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(opp->src[n_IRQ].ipvp & 0x40000000) |
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(val & 0x800F00FF);
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openpic_update_irq(opp, n_IRQ);
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DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
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n_IRQ, val, opp->src[n_IRQ].ipvp);
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break;
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case IRQ_IDE:
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tmp = val & 0xC0000000;
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tmp |= val & ((1ULL << MAX_CPU) - 1);
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opp->src[n_IRQ].ide = tmp;
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DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
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break;
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}
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tmp = val & 0xC0000000;
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tmp |= val & ((1ULL << MAX_CPU) - 1);
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opp->src[n_IRQ].ide = tmp;
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DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
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}
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static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
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{
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/* NOTE: not fully accurate for special IRQs, but simple and sufficient */
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/* ACTIVITY bit is read-only */
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opp->src[n_IRQ].ipvp = (opp->src[n_IRQ].ipvp & 0x40000000)
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| (val & 0x800F00FF);
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openpic_update_irq(opp, n_IRQ);
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DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
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opp->src[n_IRQ].ipvp);
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}
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#if 0 // Code provision for Intel model
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@ -535,10 +530,10 @@ static void write_doorbell_register (penpic_t *opp, int n_dbl,
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{
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switch (offset) {
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case DBL_IVPR_OFFSET:
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write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
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write_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl, value);
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break;
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case DBL_IDE_OFFSET:
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write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
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write_IRQreg_ide(opp, IRQ_DBL0 + n_dbl, value);
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break;
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case DBL_DMR_OFFSET:
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opp->doorbells[n_dbl].dmr = value;
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@ -576,10 +571,10 @@ static void write_mailbox_register (openpic_t *opp, int n_mbx,
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opp->mailboxes[n_mbx].mbr = value;
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break;
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case MBX_IVPR_OFFSET:
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write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value);
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write_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx, value);
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break;
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case MBX_DMR_OFFSET:
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write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value);
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write_IRQreg_ide(opp, IRQ_MBX0 + n_mbx, value);
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break;
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}
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}
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@ -636,7 +631,7 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
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{
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int idx;
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idx = (addr - 0x10A0) >> 4;
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write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP, val);
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write_IRQreg_ipvp(opp, opp->irq_ipi0 + idx, val);
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}
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break;
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case 0x10E0: /* SPVE */
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@ -729,10 +724,10 @@ static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
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opp->timers[idx].tibc = val;
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break;
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case 0x20: /* TIVP */
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write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP, val);
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write_IRQreg_ipvp(opp, opp->irq_tim0 + idx, val);
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break;
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case 0x30: /* TIDE */
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write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE, val);
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write_IRQreg_ide(opp, opp->irq_tim0 + idx, val);
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break;
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}
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}
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@ -782,10 +777,10 @@ static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
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idx = addr >> 5;
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if (addr & 0x10) {
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/* EXDE / IFEDE / IEEDE */
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write_IRQreg(opp, idx, IRQ_IDE, val);
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write_IRQreg_ide(opp, idx, val);
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} else {
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/* EXVP / IFEVP / IEEVP */
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write_IRQreg(opp, idx, IRQ_IPVP, val);
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write_IRQreg_ipvp(opp, idx, val);
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}
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}
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@ -835,8 +830,8 @@ static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
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case 0x70:
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idx = (addr - 0x40) >> 4;
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/* we use IDE as mask which CPUs to deliver the IPI to still. */
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write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE,
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opp->src[opp->irq_ipi0 + idx].ide | val);
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write_IRQreg_ide(opp, opp->irq_ipi0 + idx,
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opp->src[opp->irq_ipi0 + idx].ide | val);
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openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
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openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
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break;
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@ -1330,13 +1325,13 @@ static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t va
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mpp->timers[idx].tibc = val;
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break;
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case 0x20: /* GTIVPR */
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write_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IPVP, val);
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write_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx, val);
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break;
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case 0x30: /* GTIDR & TFRR */
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if ((addr & 0xF0) == 0xF0)
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mpp->dst[cpu].tfrr = val;
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else
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write_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IDE, val);
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write_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx, val);
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break;
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}
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}
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@ -1391,10 +1386,10 @@ static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
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idx += (addr & 0xFFF0) >> 5;
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if (addr & 0x10) {
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/* EXDE / IFEDE / IEEDE */
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write_IRQreg(mpp, idx, IRQ_IDE, val);
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write_IRQreg_ide(mpp, idx, val);
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} else {
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/* EXVP / IFEVP / IEEVP */
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write_IRQreg(mpp, idx, IRQ_IPVP, val);
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write_IRQreg_ipvp(mpp, idx, val);
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}
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}
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}
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@ -1441,10 +1436,10 @@ static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
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idx += (addr & 0xFFF0) >> 5;
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if (addr & 0x10) {
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/* EXDE / IFEDE / IEEDE */
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write_IRQreg(mpp, idx, IRQ_IDE, val);
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write_IRQreg_ide(mpp, idx, val);
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} else {
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/* EXVP / IFEVP / IEEVP */
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write_IRQreg(mpp, idx, IRQ_IPVP, val);
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write_IRQreg_ipvp(mpp, idx, val);
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}
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}
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}
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@ -1491,10 +1486,10 @@ static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
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idx += (addr & 0xFFF0) >> 5;
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if (addr & 0x10) {
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/* EXDE / IFEDE / IEEDE */
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write_IRQreg(mpp, idx, IRQ_IDE, val);
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write_IRQreg_ide(mpp, idx, val);
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} else {
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/* EXVP / IFEVP / IEEVP */
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write_IRQreg(mpp, idx, IRQ_IPVP, val);
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write_IRQreg_ipvp(mpp, idx, val);
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}
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}
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}
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@ -1541,10 +1536,10 @@ static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
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idx += (addr & 0xFFF0) >> 5;
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if (addr & 0x10) {
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/* EXDE / IFEDE / IEEDE */
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write_IRQreg(mpp, idx, IRQ_IDE, val);
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write_IRQreg_ide(mpp, idx, val);
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} else {
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/* EXVP / IFEVP / IEEVP */
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write_IRQreg(mpp, idx, IRQ_IPVP, val);
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write_IRQreg_ipvp(mpp, idx, val);
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}
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}
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}
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