ppc patch queue 2019-04-09
This is a small, hard freeze, pull request which fixes a regression on the pseries machine handling of PCI-E extended config space accesses. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAlysQxQACgkQbDjKyiDZ s5KZkxAAgVi1n2oBroYnXwqJoalm5WYntJhkKBzmQqLFaOFqnhK7110eQ/Vyc2OZ rn9QUODczxuUH0McdW3McfXa0J/ZHP9sZhmtl06okfVodT8Yx3UXq11pYFzRbhrx SWpCzgWK04SfDsKxak5d9uah/p6vOkmojCLI8+s0npb4uv3hBpOScQ3OCrwyqvZL R4715SiqV2T2J4BBhBpsXNE4NRFKuA3AQlKDqt15iWHpKkk11NMscXP+n5cKsIUl ZXcjSByYNhAGHUCMZvK1Oht64+FSnkZg1Z7l3SWvLT5wxyHHvfuFBAxlSysveqvE 7quWpoHsjMn2sgyolUM4PY2IdEFmgnxBN4nYJVxhAQmgRteIAa8ybT/yYEJA9gx2 Dyl7D5eBW9SAwEfETa8Ilf0JqHeWwZcs7hY8za/si+CQ9syCI/TMI6PYpUY7PUqx UjeyilcmFfzloS5Ex9GYFYQVICJ1EEczUZbTJgIcSizjJFNyi7tgAofEydrGon9e 98HMCz9MIlOzINNf0gleS5UsaKnQGQtusPuplN8/9kAhhgEMYLCwFgHyNJb8BmFa SBy4m18P5idDC+ljh7bQ043RJwrY4+JDO6+7z/lU19Im7ZYz9EZuIHGobmWf0jg0 AQSuR7PLbG92NwYHjTU/JDSNomLM+B+QOfr/Qg81cQ08w/41oPo= =56np -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190409' into staging ppc patch queue 2019-04-09 This is a small, hard freeze, pull request which fixes a regression on the pseries machine handling of PCI-E extended config space accesses. # gpg: Signature made Tue 09 Apr 2019 08:00:36 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-4.0-20190409: spapr_pci: Fix extended config space accesses pci: Allow PCI bus subtypes to support extended config space accesses Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
120cba7ff1
24
hw/pci/pci.c
24
hw/pci/pci.c
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@ -147,6 +147,11 @@ static uint16_t pcibus_numa_node(PCIBus *bus)
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return NUMA_NODE_UNASSIGNED;
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}
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static bool pcibus_allows_extended_config_space(PCIBus *bus)
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{
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return false;
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}
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static void pci_bus_class_init(ObjectClass *klass, void *data)
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{
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BusClass *k = BUS_CLASS(klass);
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@ -162,6 +167,7 @@ static void pci_bus_class_init(ObjectClass *klass, void *data)
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pbc->is_root = pcibus_is_root;
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pbc->bus_num = pcibus_num;
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pbc->numa_node = pcibus_numa_node;
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pbc->allows_extended_config_space = pcibus_allows_extended_config_space;
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}
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static const TypeInfo pci_bus_info = {
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@ -182,9 +188,22 @@ static const TypeInfo conventional_pci_interface_info = {
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.parent = TYPE_INTERFACE,
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};
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static bool pciebus_allows_extended_config_space(PCIBus *bus)
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{
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return true;
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}
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static void pcie_bus_class_init(ObjectClass *klass, void *data)
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{
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PCIBusClass *pbc = PCI_BUS_CLASS(klass);
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pbc->allows_extended_config_space = pciebus_allows_extended_config_space;
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}
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static const TypeInfo pcie_bus_info = {
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.name = TYPE_PCIE_BUS,
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.parent = TYPE_PCI_BUS,
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.class_init = pcie_bus_class_init,
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};
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static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
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@ -401,6 +420,11 @@ bool pci_bus_is_root(PCIBus *bus)
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return PCI_BUS_GET_CLASS(bus)->is_root(bus);
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}
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bool pci_bus_allows_extended_config_space(PCIBus *bus)
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{
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return PCI_BUS_GET_CLASS(bus)->allows_extended_config_space(bus);
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}
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void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
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const char *name,
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MemoryRegion *address_space_mem,
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@ -54,7 +54,7 @@ static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
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static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit)
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{
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if (*limit > PCI_CONFIG_SPACE_SIZE) {
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if (!pci_bus_is_express(bus)) {
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if (!pci_bus_allows_extended_config_space(bus)) {
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*limit = PCI_CONFIG_SPACE_SIZE;
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return;
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}
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@ -1638,6 +1638,28 @@ static void spapr_phb_unrealize(DeviceState *dev, Error **errp)
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memory_region_del_subregion(get_system_memory(), &sphb->mem32window);
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}
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static bool spapr_phb_allows_extended_config_space(PCIBus *bus)
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{
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SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(BUS(bus)->parent);
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return sphb->pcie_ecs;
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}
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static void spapr_phb_root_bus_class_init(ObjectClass *klass, void *data)
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{
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PCIBusClass *pbc = PCI_BUS_CLASS(klass);
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pbc->allows_extended_config_space = spapr_phb_allows_extended_config_space;
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}
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#define TYPE_SPAPR_PHB_ROOT_BUS "spapr-pci-host-bridge-root-bus"
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static const TypeInfo spapr_phb_root_bus_info = {
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.name = TYPE_SPAPR_PHB_ROOT_BUS,
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.parent = TYPE_PCI_BUS,
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.class_init = spapr_phb_root_bus_class_init,
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};
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static void spapr_phb_realize(DeviceState *dev, Error **errp)
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{
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/* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
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@ -1739,10 +1761,11 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
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memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
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&sphb->iowindow);
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bus = pci_register_root_bus(dev, NULL,
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bus = pci_register_root_bus(dev, "pci.0",
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pci_spapr_set_irq, pci_spapr_map_irq, sphb,
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&sphb->memspace, &sphb->iospace,
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PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
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PCI_DEVFN(0, 0), PCI_NUM_PINS,
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TYPE_SPAPR_PHB_ROOT_BUS);
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phb->bus = bus;
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qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL);
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@ -2325,6 +2348,7 @@ void spapr_pci_rtas_init(void)
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static void spapr_pci_register_types(void)
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{
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type_register_static(&spapr_phb_info);
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type_register_static(&spapr_phb_root_bus_info);
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}
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type_init(spapr_pci_register_types)
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@ -396,6 +396,8 @@ typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
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bool pci_bus_is_express(PCIBus *bus);
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bool pci_bus_is_root(PCIBus *bus);
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bool pci_bus_allows_extended_config_space(PCIBus *bus);
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void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
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const char *name,
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MemoryRegion *address_space_mem,
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@ -18,6 +18,7 @@ typedef struct PCIBusClass {
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bool (*is_root)(PCIBus *bus);
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int (*bus_num)(PCIBus *bus);
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uint16_t (*numa_node)(PCIBus *bus);
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bool (*allows_extended_config_space)(PCIBus *bus);
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} PCIBusClass;
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struct PCIBus {
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