target/arm: Implement MVE VMOV to/from 2 general-purpose registers
Implement the MVE VMOV forms that move data between 2 general-purpose registers and 2 32-bit lanes in a vector register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -136,6 +136,10 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ....... @vldr_vstr \
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VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \
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VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \
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size=2 p=1
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size=2 p=1
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# Moves between 2 32-bit vector lanes and 2 general purpose registers
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VMOV_to_2gp 1110 1100 0 . 00 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=%qd
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VMOV_from_2gp 1110 1100 0 . 01 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=%qd
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# Vector 2-op
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# Vector 2-op
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VAND 1110 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz
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VAND 1110 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz
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VBIC 1110 1111 0 . 01 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz
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VBIC 1110 1111 0 . 01 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz
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@ -49,6 +49,7 @@ void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
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void clear_eci_state(DisasContext *s);
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void clear_eci_state(DisasContext *s);
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bool mve_eci_check(DisasContext *s);
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bool mve_eci_check(DisasContext *s);
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void mve_update_and_store_eci(DisasContext *s);
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void mve_update_and_store_eci(DisasContext *s);
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bool mve_skip_vmov(DisasContext *s, int vn, int index, int size);
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static inline TCGv_i32 load_cpu_offset(int offset)
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static inline TCGv_i32 load_cpu_offset(int offset)
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{
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{
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@ -1507,3 +1507,88 @@ static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn)
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DO_VABAV(VABAV_S, vabavs)
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DO_VABAV(VABAV_S, vabavs)
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DO_VABAV(VABAV_U, vabavu)
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DO_VABAV(VABAV_U, vabavu)
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static bool trans_VMOV_to_2gp(DisasContext *s, arg_VMOV_to_2gp *a)
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{
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/*
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* VMOV two 32-bit vector lanes to two general-purpose registers.
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* This insn is not predicated but it is subject to beat-wise
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* execution if it is not in an IT block. For us this means
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* only that if PSR.ECI says we should not be executing the beat
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* corresponding to the lane of the vector register being accessed
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* then we should skip perfoming the move, and that we need to do
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* the usual check for bad ECI state and advance of ECI state.
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* (If PSR.ECI is non-zero then we cannot be in an IT block.)
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*/
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TCGv_i32 tmp;
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int vd;
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if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) ||
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a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15 ||
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a->rt == a->rt2) {
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/* Rt/Rt2 cases are UNPREDICTABLE */
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return false;
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}
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if (!mve_eci_check(s) || !vfp_access_check(s)) {
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return true;
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}
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/* Convert Qreg index to Dreg for read_neon_element32() etc */
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vd = a->qd * 2;
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if (!mve_skip_vmov(s, vd, a->idx, MO_32)) {
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tmp = tcg_temp_new_i32();
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read_neon_element32(tmp, vd, a->idx, MO_32);
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store_reg(s, a->rt, tmp);
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}
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if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) {
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tmp = tcg_temp_new_i32();
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read_neon_element32(tmp, vd + 1, a->idx, MO_32);
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store_reg(s, a->rt2, tmp);
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}
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mve_update_and_store_eci(s);
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return true;
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}
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static bool trans_VMOV_from_2gp(DisasContext *s, arg_VMOV_to_2gp *a)
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{
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/*
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* VMOV two general-purpose registers to two 32-bit vector lanes.
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* This insn is not predicated but it is subject to beat-wise
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* execution if it is not in an IT block. For us this means
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* only that if PSR.ECI says we should not be executing the beat
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* corresponding to the lane of the vector register being accessed
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* then we should skip perfoming the move, and that we need to do
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* the usual check for bad ECI state and advance of ECI state.
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* (If PSR.ECI is non-zero then we cannot be in an IT block.)
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*/
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TCGv_i32 tmp;
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int vd;
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if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) ||
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a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15) {
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/* Rt/Rt2 cases are UNPREDICTABLE */
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return false;
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}
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if (!mve_eci_check(s) || !vfp_access_check(s)) {
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return true;
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}
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/* Convert Qreg idx to Dreg for read_neon_element32() etc */
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vd = a->qd * 2;
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if (!mve_skip_vmov(s, vd, a->idx, MO_32)) {
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tmp = load_reg(s, a->rt);
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write_neon_element32(tmp, vd, a->idx, MO_32);
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tcg_temp_free_i32(tmp);
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}
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if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) {
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tmp = load_reg(s, a->rt2);
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write_neon_element32(tmp, vd + 1, a->idx, MO_32);
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tcg_temp_free_i32(tmp);
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}
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mve_update_and_store_eci(s);
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return true;
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}
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@ -581,7 +581,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
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return true;
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return true;
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}
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}
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static bool mve_skip_vmov(DisasContext *s, int vn, int index, int size)
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bool mve_skip_vmov(DisasContext *s, int vn, int index, int size)
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{
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{
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/*
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/*
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* In a CPU with MVE, the VMOV (vector lane to general-purpose register)
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* In a CPU with MVE, the VMOV (vector lane to general-purpose register)
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