target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3
This is part of a reorganization to the set of mmu_idx. The EL3 regime only has a single stage translation, and is always secure. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -2908,7 +2908,7 @@ typedef enum ARMMMUIdx {
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ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
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ARMMMUIdx_E10_1 = 1 | ARM_MMU_IDX_A,
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ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
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ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
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ARMMMUIdx_SE3 = 3 | ARM_MMU_IDX_A,
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ARMMMUIdx_SE10_0 = 4 | ARM_MMU_IDX_A,
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ARMMMUIdx_SE10_1 = 5 | ARM_MMU_IDX_A,
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ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A,
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@ -2934,7 +2934,7 @@ typedef enum ARMMMUIdxBit {
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ARMMMUIdxBit_E10_0 = 1 << 0,
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ARMMMUIdxBit_E10_1 = 1 << 1,
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ARMMMUIdxBit_S1E2 = 1 << 2,
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ARMMMUIdxBit_S1E3 = 1 << 3,
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ARMMMUIdxBit_SE3 = 1 << 3,
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ARMMMUIdxBit_SE10_0 = 1 << 4,
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ARMMMUIdxBit_SE10_1 = 1 << 5,
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ARMMMUIdxBit_Stage2 = 1 << 6,
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@ -3187,7 +3187,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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/* stage 1 current state PL1: ATS1CPR, ATS1CPW */
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switch (el) {
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case 3:
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mmu_idx = ARMMMUIdx_S1E3;
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mmu_idx = ARMMMUIdx_SE3;
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break;
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case 2:
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mmu_idx = ARMMMUIdx_Stage1_E1;
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@ -3269,7 +3269,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
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mmu_idx = ARMMMUIdx_S1E2;
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break;
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case 6: /* AT S1E3R, AT S1E3W */
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mmu_idx = ARMMMUIdx_S1E3;
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mmu_idx = ARMMMUIdx_SE3;
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break;
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default:
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g_assert_not_reached();
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@ -4013,7 +4013,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
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ARMCPU *cpu = env_archcpu(env);
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CPUState *cs = CPU(cpu);
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tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3);
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tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
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}
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static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -4038,7 +4038,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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CPUState *cs = env_cpu(env);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
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}
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static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -4066,7 +4066,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
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CPUState *cs = CPU(cpu);
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3);
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tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
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}
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static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -4115,7 +4115,7 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
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ARMMMUIdxBit_S1E3);
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ARMMMUIdxBit_SE3);
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}
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static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -8713,7 +8713,7 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
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case ARMMMUIdx_Stage2:
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case ARMMMUIdx_S1E2:
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return 2;
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case ARMMMUIdx_S1E3:
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case ARMMMUIdx_SE3:
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return 3;
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case ARMMMUIdx_SE10_0:
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return arm_el_is_aa64(env, 3) ? 1 : 3;
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@ -819,7 +819,7 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
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case ARMMMUIdx_MPriv:
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case ARMMMUIdx_MUser:
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return false;
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case ARMMMUIdx_S1E3:
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case ARMMMUIdx_SE3:
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case ARMMMUIdx_SE10_0:
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case ARMMMUIdx_SE10_1:
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case ARMMMUIdx_MSPrivNegPri:
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@ -156,7 +156,7 @@ static inline int get_a32_user_mem_index(DisasContext *s)
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case ARMMMUIdx_E10_0:
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case ARMMMUIdx_E10_1:
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return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
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case ARMMMUIdx_S1E3:
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case ARMMMUIdx_SE3:
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case ARMMMUIdx_SE10_0:
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case ARMMMUIdx_SE10_1:
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return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0);
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