ppc/xive: introduce a XiveTCTX pointer under PowerPCCPU
which will be used by the machine only when the XIVE interrupt mode is in use. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
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8fa1f4ef38
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129dbe6926
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@ -321,7 +321,7 @@ static void xive_tm_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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uint64_t value, unsigned size)
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{
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{
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PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
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PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
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XiveTCTX *tctx = XIVE_TCTX(cpu->intc);
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XiveTCTX *tctx = cpu->tctx;
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const XiveTmOp *xto;
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const XiveTmOp *xto;
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/*
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/*
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@ -360,7 +360,7 @@ static void xive_tm_write(void *opaque, hwaddr offset,
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static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
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static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
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{
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{
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PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
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PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
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XiveTCTX *tctx = XIVE_TCTX(cpu->intc);
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XiveTCTX *tctx = cpu->tctx;
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const XiveTmOp *xto;
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const XiveTmOp *xto;
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/*
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/*
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@ -1186,7 +1186,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
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CPU_FOREACH(cs) {
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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XiveTCTX *tctx = XIVE_TCTX(cpu->intc);
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XiveTCTX *tctx = cpu->tctx;
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int ring;
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int ring;
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/*
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/*
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@ -194,7 +194,12 @@ static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc)
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vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
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vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
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}
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}
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qemu_unregister_reset(spapr_cpu_reset, cpu);
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qemu_unregister_reset(spapr_cpu_reset, cpu);
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object_unparent(cpu->intc);
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if (cpu->intc) {
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object_unparent(cpu->intc);
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}
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if (cpu->tctx) {
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object_unparent(OBJECT(cpu->tctx));
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}
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cpu_remove_sync(CPU(cpu));
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cpu_remove_sync(CPU(cpu));
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object_unparent(OBJECT(cpu));
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object_unparent(OBJECT(cpu));
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}
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}
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@ -315,7 +315,7 @@ static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
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CPU_FOREACH(cs) {
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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xive_tctx_pic_print_info(XIVE_TCTX(cpu->intc), mon);
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xive_tctx_pic_print_info(cpu->tctx, mon);
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}
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}
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spapr_xive_pic_print_info(spapr->xive, mon);
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spapr_xive_pic_print_info(spapr->xive, mon);
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@ -333,13 +333,13 @@ static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
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return;
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return;
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}
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}
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cpu->intc = obj;
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cpu->tctx = XIVE_TCTX(obj);
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/*
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/*
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* (TCG) Early setting the OS CAM line for hotplugged CPUs as they
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* (TCG) Early setting the OS CAM line for hotplugged CPUs as they
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* don't beneficiate from the reset of the XIVE IRQ backend
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* don't beneficiate from the reset of the XIVE IRQ backend
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*/
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*/
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spapr_xive_set_tctx_os_cam(XIVE_TCTX(obj));
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spapr_xive_set_tctx_os_cam(cpu->tctx);
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}
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}
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static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
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static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
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@ -355,7 +355,7 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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/* (TCG) Set the OS CAM line of the thread interrupt context. */
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/* (TCG) Set the OS CAM line of the thread interrupt context. */
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spapr_xive_set_tctx_os_cam(XIVE_TCTX(cpu->intc));
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spapr_xive_set_tctx_os_cam(cpu->tctx);
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}
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}
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}
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}
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@ -1177,6 +1177,7 @@ do { \
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typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
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typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
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typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
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typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
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typedef struct XiveTCTX XiveTCTX;
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/**
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/**
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* PowerPCCPU:
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* PowerPCCPU:
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@ -1196,6 +1197,7 @@ struct PowerPCCPU {
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uint32_t compat_pvr;
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uint32_t compat_pvr;
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PPCVirtualHypervisor *vhyp;
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PPCVirtualHypervisor *vhyp;
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Object *intc;
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Object *intc;
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XiveTCTX *tctx;
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void *machine_data;
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void *machine_data;
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int32_t node_id; /* NUMA node this CPU belongs to */
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int32_t node_id; /* NUMA node this CPU belongs to */
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PPCHash64Options *hash64_opts;
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PPCHash64Options *hash64_opts;
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