hw/intc/arm_gic_common.c: Reset all registers
The arm_gic_common reset function was missing reset code for several of the GIC's state fields: * bpr[] * abpr[] * priority1[] * priority2[] * sgi_pending[] * irq_target[] (SMP configurations only) These probably went unnoticed because most guests will either never touch them, or will write to them in the process of configuring the GIC before enabling interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1435602345-32210-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -123,7 +123,7 @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp)
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static void arm_gic_common_reset(DeviceState *dev)
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{
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GICState *s = ARM_GIC_COMMON(dev);
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int i;
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int i, j;
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memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
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for (i = 0 ; i < s->num_cpu; i++) {
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if (s->revision == REV_11MPCORE) {
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@ -135,15 +135,30 @@ static void arm_gic_common_reset(DeviceState *dev)
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s->running_irq[i] = 1023;
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s->running_priority[i] = 0x100;
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s->cpu_ctlr[i] = 0;
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s->bpr[i] = GIC_MIN_BPR;
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s->abpr[i] = GIC_MIN_ABPR;
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for (j = 0; j < GIC_INTERNAL; j++) {
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s->priority1[j][i] = 0;
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}
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for (j = 0; j < GIC_NR_SGIS; j++) {
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s->sgi_pending[j][i] = 0;
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}
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}
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for (i = 0; i < GIC_NR_SGIS; i++) {
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GIC_SET_ENABLED(i, ALL_CPU_MASK);
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GIC_SET_EDGE_TRIGGER(i);
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}
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if (s->num_cpu == 1) {
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/* For uniprocessor GICs all interrupts always target the sole CPU */
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for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
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s->priority2[i] = 0;
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}
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for (i = 0; i < GIC_MAXIRQ; i++) {
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/* For uniprocessor GICs all interrupts always target the sole CPU */
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if (s->num_cpu == 1) {
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s->irq_target[i] = 1;
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} else {
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s->irq_target[i] = 0;
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}
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}
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s->ctlr = 0;
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