s390x/tcg: store in the TB flags if AFP is enabled
We exit the TB when changing the control registers, so just like PSW bits, this should always be consistent for a TB. Using the PSW bit semantic makes things a lot easier compared to manually defining the spare, shifted bits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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@ -255,6 +255,7 @@ extern const struct VMStateDescription vmstate_s390_cpu;
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/* PSW defines */
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#undef PSW_MASK_PER
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#undef PSW_MASK_UNUSED_2
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#undef PSW_MASK_DAT
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#undef PSW_MASK_IO
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#undef PSW_MASK_EXT
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@ -273,6 +274,7 @@ extern const struct VMStateDescription vmstate_s390_cpu;
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#undef PSW_MASK_ESA_ADDR
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#define PSW_MASK_PER 0x4000000000000000ULL
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#define PSW_MASK_UNUSED_2 0x2000000000000000ULL
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#define PSW_MASK_DAT 0x0400000000000000ULL
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#define PSW_MASK_IO 0x0200000000000000ULL
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#define PSW_MASK_EXT 0x0100000000000000ULL
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@ -318,6 +320,9 @@ extern const struct VMStateDescription vmstate_s390_cpu;
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#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
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| FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
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/* we'll use some unused PSW positions to store CR flags in tb flags */
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#define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
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/* Control register 0 bits */
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#define CR0_LOWPROT 0x0000000010000000ULL
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#define CR0_SECONDARY 0x0000000004000000ULL
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@ -364,6 +369,9 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
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*pc = env->psw.addr;
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*cs_base = env->ex_value;
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*flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
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if (env->cregs[0] & CR0_AFP) {
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*flags |= FLAG_MASK_AFP;
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}
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}
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/* PER bits from control register 9 */
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