target/ppc: Use MMUAccessType in mmu-radix64.c
We must leave the 'int rwx' parameter to ppc_radix64_handle_mmu_fault for now, but will clean that up later. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-3-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson
David Gibson
parent
182357dbb6
commit
13c5fdbac6
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@ -75,71 +75,94 @@ static bool ppc_radix64_get_fully_qualified_addr(const CPUPPCState *env,
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return true;
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}
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static void ppc_radix64_raise_segi(PowerPCCPU *cpu, int rwx, vaddr eaddr)
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static void ppc_radix64_raise_segi(PowerPCCPU *cpu, MMUAccessType access_type,
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vaddr eaddr)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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if (rwx == 2) { /* Instruction Segment Interrupt */
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switch (access_type) {
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case MMU_INST_FETCH:
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/* Instruction Segment Interrupt */
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cs->exception_index = POWERPC_EXCP_ISEG;
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} else { /* Data Segment Interrupt */
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break;
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case MMU_DATA_STORE:
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case MMU_DATA_LOAD:
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/* Data Segment Interrupt */
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cs->exception_index = POWERPC_EXCP_DSEG;
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env->spr[SPR_DAR] = eaddr;
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break;
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default:
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g_assert_not_reached();
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}
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env->error_code = 0;
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}
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static void ppc_radix64_raise_si(PowerPCCPU *cpu, int rwx, vaddr eaddr,
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uint32_t cause)
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static void ppc_radix64_raise_si(PowerPCCPU *cpu, MMUAccessType access_type,
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vaddr eaddr, uint32_t cause)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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if (rwx == 2) { /* Instruction Storage Interrupt */
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switch (access_type) {
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case MMU_INST_FETCH:
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/* Instruction Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_ISI;
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env->error_code = cause;
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} else { /* Data Storage Interrupt */
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break;
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case MMU_DATA_STORE:
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cause |= DSISR_ISSTORE;
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/* fall through */
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case MMU_DATA_LOAD:
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/* Data Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_DSI;
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if (rwx == 1) { /* Write -> Store */
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cause |= DSISR_ISSTORE;
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}
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env->spr[SPR_DSISR] = cause;
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env->spr[SPR_DAR] = eaddr;
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env->error_code = 0;
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, int rwx, vaddr eaddr,
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hwaddr g_raddr, uint32_t cause)
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static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, MMUAccessType access_type,
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vaddr eaddr, hwaddr g_raddr, uint32_t cause)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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if (rwx == 2) { /* H Instruction Storage Interrupt */
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switch (access_type) {
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case MMU_INST_FETCH:
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/* H Instruction Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_HISI;
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env->spr[SPR_ASDR] = g_raddr;
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env->error_code = cause;
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} else { /* H Data Storage Interrupt */
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break;
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case MMU_DATA_STORE:
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cause |= DSISR_ISSTORE;
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/* fall through */
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case MMU_DATA_LOAD:
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/* H Data Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_HDSI;
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if (rwx == 1) { /* Write -> Store */
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cause |= DSISR_ISSTORE;
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}
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env->spr[SPR_HDSISR] = cause;
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env->spr[SPR_HDAR] = eaddr;
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env->spr[SPR_ASDR] = g_raddr;
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env->error_code = 0;
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break;
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default:
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g_assert_not_reached();
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}
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}
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static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
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int *fault_cause, int *prot,
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static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_type,
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uint64_t pte, int *fault_cause, int *prot,
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bool partition_scoped)
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{
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CPUPPCState *env = &cpu->env;
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int need_prot;
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/* Check Page Attributes (pte58:59) */
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if (((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO) && (rwx == 2)) {
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if ((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO && access_type == MMU_INST_FETCH) {
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/*
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* Radix PTE entries with the non-idempotent I/O attribute are treated
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* as guarded storage
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@ -159,7 +182,7 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
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}
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/* Check if requested access type is allowed */
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need_prot = prot_for_access_type(rwx);
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need_prot = prot_for_access_type(access_type);
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if (need_prot & ~*prot) { /* Page Protected for that Access */
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*fault_cause |= DSISR_PROTFAULT;
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return true;
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@ -168,15 +191,15 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
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return false;
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}
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static void ppc_radix64_set_rc(PowerPCCPU *cpu, int rwx, uint64_t pte,
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hwaddr pte_addr, int *prot)
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static void ppc_radix64_set_rc(PowerPCCPU *cpu, MMUAccessType access_type,
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uint64_t pte, hwaddr pte_addr, int *prot)
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{
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CPUState *cs = CPU(cpu);
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uint64_t npte;
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npte = pte | R_PTE_R; /* Always set reference bit */
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if (rwx == 1) { /* Store/Write */
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if (access_type == MMU_DATA_STORE) { /* Store/Write */
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npte |= R_PTE_C; /* Set change bit */
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} else {
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/*
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@ -271,7 +294,8 @@ static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
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return true;
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}
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static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, int rwx,
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static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu,
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MMUAccessType access_type,
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vaddr eaddr, hwaddr g_raddr,
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ppc_v3_pate_t pate,
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hwaddr *h_raddr, int *h_prot,
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@ -287,24 +311,25 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, int rwx,
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if (ppc_radix64_walk_tree(CPU(cpu)->as, g_raddr, pate.dw0 & PRTBE_R_RPDB,
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pate.dw0 & PRTBE_R_RPDS, h_raddr, h_page_size,
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&pte, &fault_cause, &pte_addr) ||
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ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, h_prot, true)) {
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ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, h_prot, true)) {
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if (pde_addr) { /* address being translated was that of a guest pde */
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fault_cause |= DSISR_PRTABLE_FAULT;
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}
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if (guest_visible) {
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ppc_radix64_raise_hsi(cpu, rwx, eaddr, g_raddr, fault_cause);
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ppc_radix64_raise_hsi(cpu, access_type, eaddr, g_raddr, fault_cause);
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}
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return 1;
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}
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if (guest_visible) {
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ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, h_prot);
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ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, h_prot);
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}
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return 0;
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}
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static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
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MMUAccessType access_type,
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vaddr eaddr, uint64_t pid,
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ppc_v3_pate_t pate, hwaddr *g_raddr,
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int *g_prot, int *g_page_size,
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@ -323,7 +348,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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if (offset >= size) {
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/* offset exceeds size of the process table */
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if (guest_visible) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
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ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE);
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}
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return 1;
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}
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@ -364,7 +389,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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if (ret) {
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/* No valid PTE */
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if (guest_visible) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause);
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}
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return ret;
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}
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@ -393,7 +418,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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if (ret) {
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/* No valid pte */
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if (guest_visible) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause);
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}
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return ret;
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}
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@ -407,16 +432,16 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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*g_raddr = (rpn & ~mask) | (eaddr & mask);
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}
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if (ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, g_prot, false)) {
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if (ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, g_prot, false)) {
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/* Access denied due to protection */
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if (guest_visible) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause);
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}
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return 1;
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}
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if (guest_visible) {
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ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, g_prot);
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ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, g_prot);
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}
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return 0;
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@ -439,7 +464,8 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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* | = On | Process Scoped | Scoped |
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* +-------------+----------------+---------------+
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*/
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static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,
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MMUAccessType access_type,
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bool relocation,
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hwaddr *raddr, int *psizep, int *protp,
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bool guest_visible)
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@ -453,7 +479,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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/* Virtual Mode Access - get the fully qualified address */
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if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) {
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if (guest_visible) {
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ppc_radix64_raise_segi(cpu, rwx, eaddr);
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ppc_radix64_raise_segi(cpu, access_type, eaddr);
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}
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return 1;
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}
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@ -466,13 +492,13 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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} else {
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if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
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if (guest_visible) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
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ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE);
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}
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return 1;
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}
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if (!validate_pate(cpu, lpid, &pate)) {
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if (guest_visible) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG);
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ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_R_BADCONFIG);
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}
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return 1;
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}
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@ -490,7 +516,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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* - Translates an effective address to a guest real address.
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*/
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if (relocation) {
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int ret = ppc_radix64_process_scoped_xlate(cpu, rwx, eaddr, pid,
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int ret = ppc_radix64_process_scoped_xlate(cpu, access_type, eaddr, pid,
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pate, &g_raddr, &prot,
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&psize, guest_visible);
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if (ret) {
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@ -513,9 +539,10 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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if (lpid || !msr_hv) {
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int ret;
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ret = ppc_radix64_partition_scoped_xlate(cpu, rwx, eaddr, g_raddr,
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pate, raddr, &prot, &psize,
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false, guest_visible);
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ret = ppc_radix64_partition_scoped_xlate(cpu, access_type, eaddr,
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g_raddr, pate, raddr,
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&prot, &psize, false,
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guest_visible);
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if (ret) {
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return ret;
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}
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@ -536,12 +563,14 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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CPUPPCState *env = &cpu->env;
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int page_size, prot;
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bool relocation;
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MMUAccessType access_type;
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hwaddr raddr;
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assert(!(msr_hv && cpu->vhyp));
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assert((rwx == 0) || (rwx == 1) || (rwx == 2));
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access_type = rwx;
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relocation = ((rwx == 2) && (msr_ir == 1)) || ((rwx != 2) && (msr_dr == 1));
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relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);
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/* HV or virtual hypervisor Real Mode Access */
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if (!relocation && (msr_hv || cpu->vhyp)) {
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/* In real mode top 4 effective addr bits (mostly) ignored */
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@ -570,7 +599,7 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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}
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/* Translate eaddr to raddr (where raddr is addr qemu needs for access) */
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if (ppc_radix64_xlate(cpu, eaddr, rwx, relocation, &raddr,
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if (ppc_radix64_xlate(cpu, eaddr, access_type, relocation, &raddr,
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&page_size, &prot, true)) {
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return 1;
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}
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