target/xtensa: add internal/noop SRs and opcodes
Add two special registers: MMID and DDR: - MMID is write-only and the only side effect of writing to it is output to the trace port, which is not emulated; - DDR is only accessible in debug mode, which is not emulated. Add two debug-mode-only opcodes: - rfdd and rfdo do return from the debug mode, which is not emulated. Add three internal opcodes for full MMU: - hwwdtlba and hwwitlba are the internal opcodes that write a value into autoupdate DTLB or ITLB entry. - ldpte is internal opcode that loads PTE entry that covers the most recent page fault address. None of these three opcodes may appear in a valid instruction. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -127,6 +127,7 @@ enum {
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WINDOW_BASE = 72,
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WINDOW_START = 73,
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PTEVADDR = 83,
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MMID = 89,
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RASID = 90,
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ITLBCFG = 91,
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DTLBCFG = 92,
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@ -134,6 +135,7 @@ enum {
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MEMCTL = 97,
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CACHEATTR = 98,
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ATOMCTL = 99,
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DDR = 104,
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IBREAKA = 128,
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DBREAKA = 144,
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DBREAKC = 160,
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@ -135,6 +135,7 @@ static const XtensaReg sregnames[256] = {
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[WINDOW_START] = XTENSA_REG("WINDOW_START",
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XTENSA_OPTION_WINDOWED_REGISTER),
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[PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
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[MMID] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL),
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[RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
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[ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
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[DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
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@ -142,6 +143,7 @@ static const XtensaReg sregnames[256] = {
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[MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL),
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[CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
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[ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
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[DDR] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG),
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[IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
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[IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
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[DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
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@ -2761,6 +2763,12 @@ static const XtensaOpcodeOps core_ops[] = {
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}, {
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.name = "extw",
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.translate = translate_nop,
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}, {
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.name = "hwwdtlba",
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.translate = translate_ill,
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}, {
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.name = "hwwitlba",
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.translate = translate_ill,
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}, {
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.name = "idtlb",
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.translate = translate_itlb,
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@ -2846,6 +2854,9 @@ static const XtensaOpcodeOps core_ops[] = {
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.name = "ldinc",
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.translate = translate_mac16,
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.par = (const uint32_t[]){MAC16_NONE, 0, 0, 4},
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}, {
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.name = "ldpte",
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.translate = translate_ill,
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}, {
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.name = "loop",
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.translate = translate_loop,
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@ -3264,9 +3275,15 @@ static const XtensaOpcodeOps core_ops[] = {
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}, {
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.name = "retw.n",
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.translate = translate_retw,
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}, {
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.name = "rfdd",
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.translate = translate_ill,
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}, {
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.name = "rfde",
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.translate = translate_rfde,
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}, {
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.name = "rfdo",
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.translate = translate_ill,
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}, {
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.name = "rfe",
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.translate = translate_rfe,
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@ -3367,6 +3384,10 @@ static const XtensaOpcodeOps core_ops[] = {
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.name = "rsr.dbreakc1",
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.translate = translate_rsr,
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.par = (const uint32_t[]){DBREAKC + 1},
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}, {
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.name = "rsr.ddr",
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.translate = translate_rsr,
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.par = (const uint32_t[]){DDR},
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}, {
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.name = "rsr.debugcause",
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.translate = translate_rsr,
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@ -3802,6 +3823,10 @@ static const XtensaOpcodeOps core_ops[] = {
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.name = "wsr.dbreakc1",
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.translate = translate_wsr,
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.par = (const uint32_t[]){DBREAKC + 1},
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}, {
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.name = "wsr.ddr",
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.translate = translate_wsr,
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.par = (const uint32_t[]){DDR},
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}, {
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.name = "wsr.debugcause",
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.translate = translate_wsr,
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@ -3994,6 +4019,10 @@ static const XtensaOpcodeOps core_ops[] = {
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.name = "wsr.misc3",
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.translate = translate_wsr,
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.par = (const uint32_t[]){MISC + 3},
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}, {
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.name = "wsr.mmid",
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.translate = translate_wsr,
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.par = (const uint32_t[]){MMID},
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}, {
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.name = "wsr.prid",
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.translate = translate_wsr,
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@ -4121,6 +4150,10 @@ static const XtensaOpcodeOps core_ops[] = {
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.name = "xsr.dbreakc1",
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.translate = translate_xsr,
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.par = (const uint32_t[]){DBREAKC + 1},
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}, {
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.name = "xsr.ddr",
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.translate = translate_xsr,
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.par = (const uint32_t[]){DDR},
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}, {
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.name = "xsr.debugcause",
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.translate = translate_xsr,
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