target/sh4: movua.l is an SH4-A only instruction
At the same time change the comment describing the instruction the same way than other instruction, so that the code is easier to read and search. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -1501,17 +1501,21 @@ static void _decode_opc(DisasContext * ctx)
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}
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}
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ctx->has_movcal = 1;
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ctx->has_movcal = 1;
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return;
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return;
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case 0x40a9:
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case 0x40a9: /* movua.l @Rm,R0 */
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/* MOVUA.L @Rm,R0 (Rm) -> R0
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/* Load non-boundary-aligned data */
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Load non-boundary-aligned data */
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if (ctx->features & SH_FEATURE_SH4A) {
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tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
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tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
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return;
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return;
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case 0x40e9:
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}
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/* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm
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break;
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Load non-boundary-aligned data */
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case 0x40e9: /* movua.l @Rm+,R0 */
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/* Load non-boundary-aligned data */
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if (ctx->features & SH_FEATURE_SH4A) {
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tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
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tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
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tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
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tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
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return;
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return;
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}
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break;
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case 0x0029: /* movt Rn */
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case 0x0029: /* movt Rn */
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tcg_gen_mov_i32(REG(B11_8), cpu_sr_t);
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tcg_gen_mov_i32(REG(B11_8), cpu_sr_t);
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return;
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return;
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