target/arm: Implement SVE2 WHILERW, WHILEWR
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -702,6 +702,9 @@ CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
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# SVE integer compare scalar count and limit
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# SVE integer compare scalar count and limit
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WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 lt:1 rn:5 eq:1 rd:4
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WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 lt:1 rn:5 eq:1 rd:4
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# SVE2 pointer conflict compare
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WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4
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### SVE Integer Wide Immediate - Unpredicated Group
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### SVE Integer Wide Immediate - Unpredicated Group
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# SVE broadcast floating-point immediate (unpredicated)
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# SVE broadcast floating-point immediate (unpredicated)
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@ -3218,6 +3218,73 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
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return true;
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return true;
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}
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}
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static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
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{
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TCGv_i64 op0, op1, diff, t1, tmax;
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TCGv_i32 t2, t3;
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TCGv_ptr ptr;
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unsigned vsz = vec_full_reg_size(s);
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unsigned desc = 0;
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if (!dc_isar_feature(aa64_sve2, s)) {
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return false;
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}
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if (!sve_access_check(s)) {
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return true;
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}
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op0 = read_cpu_reg(s, a->rn, 1);
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op1 = read_cpu_reg(s, a->rm, 1);
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tmax = tcg_const_i64(vsz);
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diff = tcg_temp_new_i64();
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if (a->rw) {
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/* WHILERW */
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/* diff = abs(op1 - op0), noting that op0/1 are unsigned. */
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t1 = tcg_temp_new_i64();
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tcg_gen_sub_i64(diff, op0, op1);
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tcg_gen_sub_i64(t1, op1, op0);
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tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, diff, t1);
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tcg_temp_free_i64(t1);
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/* Round down to a multiple of ESIZE. */
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tcg_gen_andi_i64(diff, diff, -1 << a->esz);
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/* If op1 == op0, diff == 0, and the condition is always true. */
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tcg_gen_movcond_i64(TCG_COND_EQ, diff, op0, op1, tmax, diff);
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} else {
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/* WHILEWR */
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tcg_gen_sub_i64(diff, op1, op0);
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/* Round down to a multiple of ESIZE. */
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tcg_gen_andi_i64(diff, diff, -1 << a->esz);
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/* If op0 >= op1, diff <= 0, the condition is always true. */
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tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, tmax, diff);
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}
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/* Bound to the maximum. */
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tcg_gen_umin_i64(diff, diff, tmax);
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tcg_temp_free_i64(tmax);
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/* Since we're bounded, pass as a 32-bit type. */
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t2 = tcg_temp_new_i32();
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tcg_gen_extrl_i64_i32(t2, diff);
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tcg_temp_free_i64(diff);
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desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
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desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
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t3 = tcg_const_i32(desc);
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ptr = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
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gen_helper_sve_whilel(t2, ptr, t2, t3);
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do_pred_flags(t2);
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tcg_temp_free_ptr(ptr);
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tcg_temp_free_i32(t2);
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tcg_temp_free_i32(t3);
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return true;
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}
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/*
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/*
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*** SVE Integer Wide Immediate - Unpredicated Group
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*** SVE Integer Wide Immediate - Unpredicated Group
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*/
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*/
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