Sun4c cleanups (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5568 c046a42c-6fe2-441c-8c8c-71466251a162
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hw/sun4m.c
15
hw/sun4m.c
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@ -99,7 +99,7 @@ struct sun4m_hwdef {
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long vram_size, nvram_size;
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long vram_size, nvram_size;
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// IRQ numbers are not PIL ones, but master interrupt controller
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// IRQ numbers are not PIL ones, but master interrupt controller
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// register bit numbers
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// register bit numbers
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int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
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int esp_irq, le_irq, clock_irq, clock1_irq;
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int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
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int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
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uint8_t nvram_machine_id;
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uint8_t nvram_machine_id;
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uint16_t machine_id;
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uint16_t machine_id;
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@ -135,12 +135,12 @@ struct sun4c_hwdef {
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
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target_phys_addr_t serial_base, fd_base;
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target_phys_addr_t serial_base, fd_base;
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
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target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
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target_phys_addr_t tcx_base, aux1_base;
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long vram_size, nvram_size;
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long vram_size, nvram_size;
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// IRQ numbers are not PIL ones, but master interrupt controller
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// IRQ numbers are not PIL ones, but master interrupt controller
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// register bit numbers
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// register bit numbers
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int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
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int esp_irq, le_irq, clock_irq, clock1_irq;
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int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
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int ser_irq, ms_kb_irq, fd_irq, me_irq;
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uint8_t nvram_machine_id;
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uint8_t nvram_machine_id;
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uint16_t machine_id;
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uint16_t machine_id;
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uint32_t iommu_version;
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uint32_t iommu_version;
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@ -1440,7 +1440,6 @@ static const struct sun4c_hwdef sun4c_hwdefs[] = {
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{
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{
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.iommu_base = 0xf8000000,
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.iommu_base = 0xf8000000,
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.tcx_base = 0xfe000000,
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.tcx_base = 0xfe000000,
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.cs_base = -1,
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.slavio_base = 0xf6000000,
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.slavio_base = 0xf6000000,
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.intctl_base = 0xf5000000,
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.intctl_base = 0xf5000000,
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.counter_base = 0xf3000000,
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.counter_base = 0xf3000000,
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@ -1451,9 +1450,7 @@ static const struct sun4c_hwdef sun4c_hwdefs[] = {
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.dma_base = 0xf8400000,
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.dma_base = 0xf8400000,
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.esp_base = 0xf8800000,
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.esp_base = 0xf8800000,
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.le_base = 0xf8c00000,
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.le_base = 0xf8c00000,
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.apc_base = -1,
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.aux1_base = 0xf7400003,
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.aux1_base = 0xf7400003,
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.aux2_base = -1,
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.vram_size = 0x00100000,
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.vram_size = 0x00100000,
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.nvram_size = 0x800,
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.nvram_size = 0x800,
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.esp_irq = 2,
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.esp_irq = 2,
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@ -1464,7 +1461,6 @@ static const struct sun4c_hwdef sun4c_hwdefs[] = {
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.ser_irq = 1,
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.ser_irq = 1,
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.fd_irq = 1,
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.fd_irq = 1,
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.me_irq = 1,
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.me_irq = 1,
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.cs_irq = -1,
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.nvram_machine_id = 0x55,
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.nvram_machine_id = 0x55,
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.machine_id = ss2_id,
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.machine_id = ss2_id,
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.max_mem = 0x10000000,
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.max_mem = 0x10000000,
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@ -1579,8 +1575,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
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slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
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slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
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serial_hds[1], serial_hds[0]);
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serial_hds[1], serial_hds[0]);
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slavio_misc = slavio_misc_init(0, hwdef->apc_base,
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slavio_misc = slavio_misc_init(0, -1, hwdef->aux1_base, -1,
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hwdef->aux1_base, hwdef->aux2_base,
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slavio_irq[hwdef->me_irq], env, &fdc_tc);
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slavio_irq[hwdef->me_irq], env, &fdc_tc);
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if (hwdef->fd_base != (target_phys_addr_t)-1) {
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if (hwdef->fd_base != (target_phys_addr_t)-1) {
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