MIPS queue
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJbM9R3AAoJENSXKoln91pl/YAH/ilTf584cQaO/senlSJjf+WC 5LR+1mjQe8uB00pNQtd9mEZnnjA9AhR2jq7rHi27hvwBiR5kZ44AIJEOAsXdLRvw a99Q8vbMfjrwqG/FyEsn+Ptz5bDhH1MA/DRg/hoNcwrRdiO5rtPjRFVej/DRv+xJ I2kZvWvxAHp5N/4TsBh7Mx/KBT/4k58mKcu4MwS2bX4554fHJ6MYdQaNngs2S2EQ qopBbO9ac6FIdJ6xu1QkHOyDuX4oF+Gm3aO0/t52bJtI8bKfISnknDgMSa2Nac31 RptC6buTkoGiBeBjFAl85B00OGJTmFW0DZrWaY5vwnS4LGrW2dYkxp/0ACMIiW0= =mXf/ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-2018-06-27' into staging MIPS queue # gpg: Signature made Wed 27 Jun 2018 19:16:23 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-2018-06-27: target/mips: Fix gdbstub to read/write 64 bit FP registers target/mips: Fix data type for offset target/mips: Update gen_flt_ldst() target/mips: Fix microMIPS on reset target/mips: Raise a RI when given fs is n/a from CTC1 hw/pci-host/xilinx-pcie: don't make "io" region be RAM hw/mips/mips_malta: don't make bios region 'nomigrate' hw/mips/boston: don't make flash region 'nomigrate' MAINTAINERS: update target-mips maintainers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
18896679aa
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@ -187,7 +187,7 @@ F: disas/microblaze.c
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MIPS
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M: Aurelien Jarno <aurelien@aurel32.net>
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M: Yongbok Kim <yongbok.kim@mips.com>
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M: Aleksandar Markovic <aleksandar.markovic@mips.com>
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S: Maintained
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F: target/mips/
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F: hw/mips/
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@ -718,7 +718,7 @@ S: Maintained
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F: hw/mips/mips_malta.c
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Mipssim
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M: Yongbok Kim <yongbok.kim@mips.com>
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M: Aleksandar Markovic <aleksandar.markovic@mips.com>
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S: Odd Fixes
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F: hw/mips/mips_mipssim.c
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F: hw/net/mipsnet.c
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@ -729,7 +729,7 @@ S: Maintained
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F: hw/mips/mips_r4k.c
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Fulong 2E
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M: Yongbok Kim <yongbok.kim@mips.com>
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M: Aleksandar Markovic <aleksandar.markovic@mips.com>
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S: Odd Fixes
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F: hw/mips/mips_fulong2e.c
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F: hw/isa/vt82c686.c
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@ -471,8 +471,7 @@ static void boston_mach_init(MachineState *machine)
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sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
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flash = g_new(MemoryRegion, 1);
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memory_region_init_rom_nomigrate(flash, NULL,
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"boston.flash", 128 * M_BYTE, &err);
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memory_region_init_rom(flash, NULL, "boston.flash", 128 * M_BYTE, &err);
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memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
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ddr = g_new(MemoryRegion, 1);
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@ -1152,7 +1152,7 @@ void mips_malta_init(MachineState *machine)
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* handled by an overlapping region as the resulting ROM code subpage
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* regions are not executable.
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*/
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memory_region_init_ram_nomigrate(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
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memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
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&error_fatal);
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if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
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FLASH_ADDRESS, BIOS_SIZE)) {
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@ -120,9 +120,8 @@ static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp)
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memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX);
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memory_region_set_enabled(&s->mmio, false);
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/* dummy I/O region */
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memory_region_init_ram_nomigrate(&s->io, OBJECT(s), "io", 16, NULL);
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memory_region_set_enabled(&s->io, false);
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/* dummy PCI I/O region (not visible to the CPU) */
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memory_region_init(&s->io, OBJECT(s), "io", 16);
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/* interrupt out */
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qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1);
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@ -39,7 +39,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
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default:
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if (env->CP0_Status & (1 << CP0St_FR)) {
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return gdb_get_regl(mem_buf,
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return gdb_get_reg64(mem_buf,
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env->active_fpu.fpr[n - 38].d);
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} else {
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return gdb_get_regl(mem_buf,
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@ -100,6 +100,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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break;
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default:
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if (env->CP0_Status & (1 << CP0St_FR)) {
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uint64_t tmp = ldq_p(mem_buf);
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env->active_fpu.fpr[n - 38].d = tmp;
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} else {
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env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
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@ -2627,6 +2627,9 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
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(env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
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break;
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default:
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if (env->insn_flags & ISA_MIPS32R6) {
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do_raise_exception(env, EXCP_RI, GETPC());
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}
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return;
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}
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restore_fp_status(env);
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@ -2112,7 +2112,7 @@ OP_ST_ATOMIC(scd,st64,ld64,0x7);
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#undef OP_ST_ATOMIC
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static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
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int base, int16_t offset)
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int base, int offset)
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{
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if (base == 0) {
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tcg_gen_movi_tl(addr, offset);
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@ -2140,7 +2140,7 @@ static target_ulong pc_relative_pc (DisasContext *ctx)
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/* Load */
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static void gen_ld(DisasContext *ctx, uint32_t opc,
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int rt, int base, int16_t offset)
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int rt, int base, int offset)
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{
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TCGv t0, t1, t2;
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int mem_idx = ctx->mem_idx;
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@ -2337,7 +2337,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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/* Store */
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static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
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int base, int16_t offset)
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int base, int offset)
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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@ -2433,11 +2433,8 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
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/* Load and store */
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static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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int base, int16_t offset)
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TCGv t0)
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{
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TCGv t0 = tcg_temp_new();
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gen_base_offset_addr(ctx, t0, base, offset);
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/* Don't do NOP if destination is zero: we must perform the actual
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memory access. */
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switch (opc) {
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default:
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MIPS_INVAL("flt_ldst");
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generate_exception_end(ctx, EXCP_RI);
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goto out;
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break;
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}
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out:
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tcg_temp_free(t0);
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}
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static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
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int rs, int16_t imm)
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{
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TCGv t0 = tcg_temp_new();
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if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
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check_cp1_enabled(ctx);
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switch (op) {
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check_insn(ctx, ISA_MIPS2);
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/* Fallthrough */
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default:
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gen_flt_ldst(ctx, op, rt, rs, imm);
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gen_base_offset_addr(ctx, t0, rs, imm);
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gen_flt_ldst(ctx, op, rt, t0);
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}
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} else {
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generate_exception_err(ctx, EXCP_CpU, 1);
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}
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tcg_temp_free(t0);
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}
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/* Arithmetic with immediate operand */
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static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
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int rt, int rs, int16_t imm)
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int rt, int rs, int imm)
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{
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target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
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env->CP0_Status |= (1 << CP0St_FR);
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}
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if (env->CP0_Config3 & (1 << CP0C3_ISA)) {
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/* microMIPS on reset when Config3.ISA == {1, 3} */
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env->hflags |= MIPS_HFLAG_M16;
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}
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/* MSA */
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if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
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msa_reset(env);
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