hw/intc: GICv3 ITS initial framework
Added register definitions relevant to ITS,implemented overall ITS device framework with stubs for ITS control and translater regions read/write,extended ITS common to handle mmio init between existing kvm device and newer qemu device. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-2-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>staging
Shashi Mallela
Peter Maydell
parent
3b8a4733d1
commit
18f6290a6a
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@ -0,0 +1,241 @@
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/*
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* ITS emulation for a GICv3-based system
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*
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* Copyright Linaro.org 2021
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*
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* Authors:
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* Shashi Mallela <shashi.mallela@linaro.org>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at your
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* option) any later version. See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/qdev-properties.h"
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#include "hw/intc/arm_gicv3_its_common.h"
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#include "gicv3_internal.h"
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#include "qom/object.h"
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#include "qapi/error.h"
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typedef struct GICv3ITSClass GICv3ITSClass;
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/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
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DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
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ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
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struct GICv3ITSClass {
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GICv3ITSCommonClass parent_class;
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void (*parent_reset)(DeviceState *dev);
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};
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static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
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uint64_t data, unsigned size,
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MemTxAttrs attrs)
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{
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return MEMTX_OK;
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}
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static bool its_writel(GICv3ITSState *s, hwaddr offset,
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uint64_t value, MemTxAttrs attrs)
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{
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bool result = true;
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return result;
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}
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static bool its_readl(GICv3ITSState *s, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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bool result = true;
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return result;
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}
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static bool its_writell(GICv3ITSState *s, hwaddr offset,
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uint64_t value, MemTxAttrs attrs)
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{
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bool result = true;
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return result;
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}
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static bool its_readll(GICv3ITSState *s, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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bool result = true;
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return result;
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}
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static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data,
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unsigned size, MemTxAttrs attrs)
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{
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GICv3ITSState *s = (GICv3ITSState *)opaque;
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bool result;
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switch (size) {
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case 4:
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result = its_readl(s, offset, data, attrs);
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break;
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case 8:
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result = its_readll(s, offset, data, attrs);
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break;
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default:
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result = false;
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break;
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}
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if (!result) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid guest read at offset " TARGET_FMT_plx
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"size %u\n", __func__, offset, size);
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/*
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* The spec requires that reserved registers are RAZ/WI;
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* so use false returns from leaf functions as a way to
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* trigger the guest-error logging but don't return it to
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* the caller, or we'll cause a spurious guest data abort.
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*/
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*data = 0;
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}
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return MEMTX_OK;
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}
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static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size, MemTxAttrs attrs)
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{
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GICv3ITSState *s = (GICv3ITSState *)opaque;
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bool result;
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switch (size) {
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case 4:
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result = its_writel(s, offset, data, attrs);
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break;
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case 8:
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result = its_writell(s, offset, data, attrs);
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break;
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default:
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result = false;
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break;
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}
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if (!result) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid guest write at offset " TARGET_FMT_plx
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"size %u\n", __func__, offset, size);
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/*
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* The spec requires that reserved registers are RAZ/WI;
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* so use false returns from leaf functions as a way to
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* trigger the guest-error logging but don't return it to
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* the caller, or we'll cause a spurious guest data abort.
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*/
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}
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return MEMTX_OK;
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}
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static const MemoryRegionOps gicv3_its_control_ops = {
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.read_with_attrs = gicv3_its_read,
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.write_with_attrs = gicv3_its_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 8,
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.impl.min_access_size = 4,
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.impl.max_access_size = 8,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const MemoryRegionOps gicv3_its_translation_ops = {
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.write_with_attrs = gicv3_its_translation_write,
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.valid.min_access_size = 2,
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.valid.max_access_size = 4,
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.impl.min_access_size = 2,
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.impl.max_access_size = 4,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
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{
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GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
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int i;
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for (i = 0; i < s->gicv3->num_cpu; i++) {
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if (!(s->gicv3->cpu[i].gicr_typer & GICR_TYPER_PLPIS)) {
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error_setg(errp, "Physical LPI not supported by CPU %d", i);
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return;
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}
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}
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gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops);
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/* set the ITS default features supported */
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s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
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GITS_TYPE_PHYSICAL);
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s->typer = FIELD_DP64(s->typer, GITS_TYPER, ITT_ENTRY_SIZE,
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ITS_ITT_ENTRY_SIZE - 1);
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s->typer = FIELD_DP64(s->typer, GITS_TYPER, IDBITS, ITS_IDBITS);
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s->typer = FIELD_DP64(s->typer, GITS_TYPER, DEVBITS, ITS_DEVBITS);
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s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIL, 1);
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s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIDBITS, ITS_CIDBITS);
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}
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static void gicv3_its_reset(DeviceState *dev)
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{
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GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
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GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
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c->parent_reset(dev);
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/* Quiescent bit reset to 1 */
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s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
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/*
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* setting GITS_BASER0.Type = 0b001 (Device)
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* GITS_BASER1.Type = 0b100 (Collection Table)
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* GITS_BASER<n>.Type,where n = 3 to 7 are 0b00 (Unimplemented)
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* GITS_BASER<0,1>.Page_Size = 64KB
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* and default translation table entry size to 16 bytes
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*/
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s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, TYPE,
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GITS_BASER_TYPE_DEVICE);
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s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, PAGESIZE,
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GITS_BASER_PAGESIZE_64K);
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s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, ENTRYSIZE,
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GITS_DTE_SIZE - 1);
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s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, TYPE,
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GITS_BASER_TYPE_COLLECTION);
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s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, PAGESIZE,
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GITS_BASER_PAGESIZE_64K);
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s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, ENTRYSIZE,
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GITS_CTE_SIZE - 1);
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}
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static Property gicv3_its_props[] = {
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DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3",
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GICv3State *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void gicv3_its_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
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dc->realize = gicv3_arm_its_realize;
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device_class_set_props(dc, gicv3_its_props);
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device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
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}
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static const TypeInfo gicv3_its_info = {
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.name = TYPE_ARM_GICV3_ITS,
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.parent = TYPE_ARM_GICV3_ITS_COMMON,
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.instance_size = sizeof(GICv3ITSState),
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.class_init = gicv3_its_class_init,
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.class_size = sizeof(GICv3ITSClass),
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};
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static void gicv3_its_register_types(void)
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{
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type_register_static(&gicv3_its_info);
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}
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type_init(gicv3_its_register_types)
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@ -50,6 +50,8 @@ static int gicv3_its_post_load(void *opaque, int version_id)
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static const VMStateDescription vmstate_its = {
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.name = "arm_gicv3_its",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_save = gicv3_its_pre_save,
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.post_load = gicv3_its_post_load,
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.priority = MIG_PRI_GICV3_ITS,
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@ -99,14 +101,15 @@ static const MemoryRegionOps gicv3_its_trans_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
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void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
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const MemoryRegionOps *tops)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
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"control", ITS_CONTROL_SIZE);
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memory_region_init_io(&s->iomem_its_translation, OBJECT(s),
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&gicv3_its_trans_ops, s,
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tops ? tops : &gicv3_its_trans_ops, s,
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"translation", ITS_TRANS_SIZE);
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/* Our two regions are always adjacent, therefore we now combine them
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@ -106,7 +106,7 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
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kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
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KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd, 0);
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gicv3_its_init_mmio(s, NULL);
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gicv3_its_init_mmio(s, NULL, NULL);
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if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CTLR)) {
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@ -24,6 +24,7 @@
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#ifndef QEMU_ARM_GICV3_INTERNAL_H
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#define QEMU_ARM_GICV3_INTERNAL_H
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#include "hw/registerfields.h"
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#include "hw/intc/arm_gicv3_common.h"
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/* Distributor registers, as offsets from the distributor base address */
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@ -67,6 +68,9 @@
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#define GICD_CTLR_E1NWF (1U << 7)
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#define GICD_CTLR_RWP (1U << 31)
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/* 16 bits EventId */
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#define GICD_TYPER_IDBITS 0xf
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/*
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* Redistributor frame offsets from RD_base
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*/
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@ -122,17 +126,17 @@
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#define GICR_WAKER_ProcessorSleep (1U << 1)
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#define GICR_WAKER_ChildrenAsleep (1U << 2)
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#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
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#define GICR_PROPBASER_ADDR_MASK (0xfffffffffULL << 12)
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#define GICR_PROPBASER_SHAREABILITY_MASK (3U << 10)
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#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
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#define GICR_PROPBASER_IDBITS_MASK (0x1f)
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FIELD(GICR_PROPBASER, IDBITS, 0, 5)
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FIELD(GICR_PROPBASER, INNERCACHE, 7, 3)
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FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2)
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FIELD(GICR_PROPBASER, PHYADDR, 12, 40)
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FIELD(GICR_PROPBASER, OUTERCACHE, 56, 3)
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#define GICR_PENDBASER_PTZ (1ULL << 62)
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#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
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#define GICR_PENDBASER_ADDR_MASK (0xffffffffULL << 16)
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#define GICR_PENDBASER_SHAREABILITY_MASK (3U << 10)
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#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
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FIELD(GICR_PENDBASER, INNERCACHE, 7, 3)
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FIELD(GICR_PENDBASER, SHAREABILITY, 10, 2)
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FIELD(GICR_PENDBASER, PHYADDR, 16, 36)
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FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3)
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FIELD(GICR_PENDBASER, PTZ, 62, 1)
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#define ICC_CTLR_EL1_CBPR (1U << 0)
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#define ICC_CTLR_EL1_EOIMODE (1U << 1)
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@ -239,6 +243,78 @@
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#define ICH_VTR_EL2_PREBITS_SHIFT 26
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#define ICH_VTR_EL2_PRIBITS_SHIFT 29
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/* ITS Registers */
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FIELD(GITS_BASER, SIZE, 0, 8)
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FIELD(GITS_BASER, PAGESIZE, 8, 2)
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FIELD(GITS_BASER, SHAREABILITY, 10, 2)
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FIELD(GITS_BASER, PHYADDR, 12, 36)
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FIELD(GITS_BASER, PHYADDRL_64K, 16, 32)
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FIELD(GITS_BASER, PHYADDRH_64K, 12, 4)
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FIELD(GITS_BASER, ENTRYSIZE, 48, 5)
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FIELD(GITS_BASER, OUTERCACHE, 53, 3)
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FIELD(GITS_BASER, TYPE, 56, 3)
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FIELD(GITS_BASER, INNERCACHE, 59, 3)
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FIELD(GITS_BASER, INDIRECT, 62, 1)
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FIELD(GITS_BASER, VALID, 63, 1)
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FIELD(GITS_CTLR, QUIESCENT, 31, 1)
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FIELD(GITS_TYPER, PHYSICAL, 0, 1)
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FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4)
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FIELD(GITS_TYPER, IDBITS, 8, 5)
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FIELD(GITS_TYPER, DEVBITS, 13, 5)
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FIELD(GITS_TYPER, SEIS, 18, 1)
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FIELD(GITS_TYPER, PTA, 19, 1)
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FIELD(GITS_TYPER, CIDBITS, 32, 4)
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FIELD(GITS_TYPER, CIL, 36, 1)
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#define GITS_BASER_PAGESIZE_4K 0
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#define GITS_BASER_PAGESIZE_16K 1
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#define GITS_BASER_PAGESIZE_64K 2
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#define GITS_BASER_TYPE_DEVICE 1ULL
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#define GITS_BASER_TYPE_COLLECTION 4ULL
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/**
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* Default features advertised by this version of ITS
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*/
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/* Physical LPIs supported */
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#define GITS_TYPE_PHYSICAL (1U << 0)
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/*
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* 12 bytes Interrupt translation Table Entry size
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* as per Table 5.3 in GICv3 spec
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* ITE Lower 8 Bytes
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* Bits: | 49 ... 26 | 25 ... 2 | 1 | 0 |
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* Values: | 1023 | IntNum | IntType | Valid |
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* ITE Higher 4 Bytes
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* Bits: | 31 ... 16 | 15 ...0 |
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* Values: | vPEID | ICID |
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*/
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#define ITS_ITT_ENTRY_SIZE 0xC
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/* 16 bits EventId */
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#define ITS_IDBITS GICD_TYPER_IDBITS
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/* 16 bits DeviceId */
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#define ITS_DEVBITS 0xF
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/* 16 bits CollectionId */
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#define ITS_CIDBITS 0xF
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/*
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* 8 bytes Device Table Entry size
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* Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits
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*/
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#define GITS_DTE_SIZE (0x8ULL)
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/*
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* 8 bytes Collection Table Entry size
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* Valid = 1 bit,RDBase = 36 bits(considering max RDBASE)
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*/
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#define GITS_CTE_SIZE (0x8ULL)
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/* Special interrupt IDs */
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#define INTID_SECURE 1020
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#define INTID_NONSECURE 1021
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@ -8,6 +8,7 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files(
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'arm_gicv3_dist.c',
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'arm_gicv3_its_common.c',
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'arm_gicv3_redist.c',
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'arm_gicv3_its.c',
|
||||
))
|
||||
softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c'))
|
||||
softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c'))
|
||||
|
|
|
|||
|
|
@ -25,17 +25,22 @@
|
|||
#include "hw/intc/arm_gicv3_common.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_ARM_GICV3_ITS "arm-gicv3-its"
|
||||
|
||||
#define ITS_CONTROL_SIZE 0x10000
|
||||
#define ITS_TRANS_SIZE 0x10000
|
||||
#define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
|
||||
|
||||
#define GITS_CTLR 0x0
|
||||
#define GITS_IIDR 0x4
|
||||
#define GITS_TYPER 0x8
|
||||
#define GITS_CBASER 0x80
|
||||
#define GITS_CWRITER 0x88
|
||||
#define GITS_CREADR 0x90
|
||||
#define GITS_BASER 0x100
|
||||
|
||||
#define GITS_TRANSLATER 0x0040
|
||||
|
||||
struct GICv3ITSState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
|
|
@ -52,6 +57,7 @@ struct GICv3ITSState {
|
|||
/* Registers */
|
||||
uint32_t ctlr;
|
||||
uint32_t iidr;
|
||||
uint64_t typer;
|
||||
uint64_t cbaser;
|
||||
uint64_t cwriter;
|
||||
uint64_t creadr;
|
||||
|
|
@ -62,7 +68,8 @@ struct GICv3ITSState {
|
|||
|
||||
typedef struct GICv3ITSState GICv3ITSState;
|
||||
|
||||
void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops);
|
||||
void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
|
||||
const MemoryRegionOps *tops);
|
||||
|
||||
#define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
|
||||
typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
|
||||
|
|
|
|||
Loading…
Reference in New Issue