tcg-arm: Use bic to implement and with constant
This greatly improves the code we can produce for deposit without armv7 support. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -145,6 +145,9 @@ static void patch_reloc(uint8_t *code_ptr, int type,
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}
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}
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#define TCG_CT_CONST_ARM 0x100
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#define TCG_CT_CONST_INV 0x200
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/* parse target specific constraints */
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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{
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@ -155,6 +158,9 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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case 'I':
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ct->ct |= TCG_CT_CONST_ARM;
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break;
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case 'K':
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ct->ct |= TCG_CT_CONST_INV;
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break;
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case 'r':
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ct->ct |= TCG_CT_REG;
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@ -279,12 +285,15 @@ static inline int tcg_target_const_match(tcg_target_long val,
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{
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int ct;
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ct = arg_ct->ct;
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if (ct & TCG_CT_CONST)
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if (ct & TCG_CT_CONST) {
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return 1;
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else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val))
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} else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
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return 1;
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else
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} else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) {
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return 1;
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} else {
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return 0;
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}
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}
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enum arm_data_opc_e {
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@ -482,6 +491,27 @@ static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst,
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}
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}
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static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv,
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TCGReg dst, TCGReg lhs, TCGArg rhs,
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bool rhs_is_const)
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{
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/* Emit either the reg,imm or reg,reg form of a data-processing insn.
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* rhs must satisfy the "rIK" constraint.
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*/
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if (rhs_is_const) {
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int rot = encode_imm(rhs);
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if (rot < 0) {
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rhs = ~rhs;
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rot = encode_imm(rhs);
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assert(rot >= 0);
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opc = opinv;
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}
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tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
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} else {
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tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
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}
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}
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static inline void tcg_out_mul32(TCGContext *s,
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int cond, int rd, int rs, int rm)
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{
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@ -1570,11 +1600,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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c = ARITH_SUB;
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goto gen_arith;
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case INDEX_op_and_i32:
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c = ARITH_AND;
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goto gen_arith;
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tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC,
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args[0], args[1], args[2], const_args[2]);
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break;
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case INDEX_op_andc_i32:
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c = ARITH_BIC;
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goto gen_arith;
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tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND,
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args[0], args[1], args[2], const_args[2]);
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break;
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case INDEX_op_or_i32:
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c = ARITH_ORR;
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goto gen_arith;
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@ -1762,8 +1794,8 @@ static const TCGTargetOpDef arm_op_defs[] = {
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{ INDEX_op_mul_i32, { "r", "r", "r" } },
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{ INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
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{ INDEX_op_muls2_i32, { "r", "r", "r", "r" } },
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{ INDEX_op_and_i32, { "r", "r", "rI" } },
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{ INDEX_op_andc_i32, { "r", "r", "rI" } },
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{ INDEX_op_and_i32, { "r", "r", "rIK" } },
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{ INDEX_op_andc_i32, { "r", "r", "rIK" } },
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{ INDEX_op_or_i32, { "r", "r", "rI" } },
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{ INDEX_op_xor_i32, { "r", "r", "rI" } },
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{ INDEX_op_neg_i32, { "r", "r" } },
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@ -49,8 +49,6 @@ typedef enum {
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#define TCG_TARGET_NB_REGS 16
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#define TCG_CT_CONST_ARM 0x100
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_R13
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#define TCG_TARGET_STACK_ALIGN 8
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