target-xtensa: implement S32NB
S32NB provides the same functionality as S32I with two exceptions. First, when its operation leaves the processor, the external transaction is marked Non-Bufferable. Second, it may not be used to write to Instruction RAM. In QEMU S32NB is equivalent to S32I. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -1965,6 +1965,17 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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}
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}
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break;
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break;
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case 5: /*S32N*/
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if (gen_window_check2(dc, RRI4_S, RRI4_T)) {
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TCGv_i32 addr = tcg_temp_new_i32();
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tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2);
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gen_load_store_alignment(dc, 2, addr, false);
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tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring);
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tcg_temp_free(addr);
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}
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break;
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default:
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default:
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RESERVED();
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RESERVED();
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break;
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break;
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