target/ppc: removed all mentions to PPC_DUMP_CPU
This feature will no longer be useful as ppc moves to using decodetree for TCG. And building with it enabled is no longer possible, due to changes in opc_handler_t. Since the last commit that mentions it happened in 2014, I think it is safe to remove it. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210531145629.21300-5-bruno.larsen@eldorado.org.br> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Bruno Larsen (billionai)
David Gibson
parent
0c5d547625
commit
1a1c9a00f3
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@ -8541,45 +8541,6 @@ static void init_ppc_proc(PowerPCCPU *cpu)
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}
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}
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#if defined(PPC_DUMP_CPU)
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static void dump_ppc_sprs(CPUPPCState *env)
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{
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ppc_spr_t *spr;
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#if !defined(CONFIG_USER_ONLY)
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uint32_t sr, sw;
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#endif
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uint32_t ur, uw;
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int i, j, n;
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printf("Special purpose registers:\n");
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for (i = 0; i < 32; i++) {
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for (j = 0; j < 32; j++) {
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n = (i << 5) | j;
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spr = &env->spr_cb[n];
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uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
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ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
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#if !defined(CONFIG_USER_ONLY)
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sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
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sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
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if (sw || sr || uw || ur) {
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printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
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(i << 5) | j, (i << 5) | j, spr->name,
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sw ? 'w' : '-', sr ? 'r' : '-',
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uw ? 'w' : '-', ur ? 'r' : '-');
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}
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#else
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if (uw || ur) {
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printf("SPR: %4d (%03x) %-8s u%c%c\n",
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(i << 5) | j, (i << 5) | j, spr->name,
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uw ? 'w' : '-', ur ? 'r' : '-');
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}
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#endif
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}
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}
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fflush(stdout);
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fflush(stderr);
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}
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#endif
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static void ppc_cpu_realize(DeviceState *dev, Error **errp)
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{
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@ -8616,172 +8577,6 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp)
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pcc->parent_realize(dev, errp);
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#if defined(PPC_DUMP_CPU)
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{
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CPUPPCState *env = &cpu->env;
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const char *mmu_model, *excp_model, *bus_model;
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switch (env->mmu_model) {
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case POWERPC_MMU_32B:
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mmu_model = "PowerPC 32";
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break;
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case POWERPC_MMU_SOFT_6xx:
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mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
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break;
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case POWERPC_MMU_SOFT_74xx:
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mmu_model = "PowerPC 74xx with software driven TLBs";
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break;
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case POWERPC_MMU_SOFT_4xx:
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mmu_model = "PowerPC 4xx with software driven TLBs";
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break;
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case POWERPC_MMU_SOFT_4xx_Z:
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mmu_model = "PowerPC 4xx with software driven TLBs "
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"and zones protections";
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break;
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case POWERPC_MMU_REAL:
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mmu_model = "PowerPC real mode only";
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break;
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case POWERPC_MMU_MPC8xx:
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mmu_model = "PowerPC MPC8xx";
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break;
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case POWERPC_MMU_BOOKE:
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mmu_model = "PowerPC BookE";
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break;
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case POWERPC_MMU_BOOKE206:
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mmu_model = "PowerPC BookE 2.06";
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break;
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case POWERPC_MMU_601:
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mmu_model = "PowerPC 601";
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break;
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#if defined(TARGET_PPC64)
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case POWERPC_MMU_64B:
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mmu_model = "PowerPC 64";
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break;
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#endif
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default:
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mmu_model = "Unknown or invalid";
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break;
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}
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switch (env->excp_model) {
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case POWERPC_EXCP_STD:
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excp_model = "PowerPC";
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break;
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case POWERPC_EXCP_40x:
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excp_model = "PowerPC 40x";
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break;
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case POWERPC_EXCP_601:
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excp_model = "PowerPC 601";
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break;
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case POWERPC_EXCP_602:
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excp_model = "PowerPC 602";
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break;
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case POWERPC_EXCP_603:
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excp_model = "PowerPC 603";
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break;
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case POWERPC_EXCP_603E:
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excp_model = "PowerPC 603e";
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break;
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case POWERPC_EXCP_604:
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excp_model = "PowerPC 604";
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break;
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case POWERPC_EXCP_7x0:
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excp_model = "PowerPC 740/750";
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break;
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case POWERPC_EXCP_7x5:
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excp_model = "PowerPC 745/755";
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break;
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case POWERPC_EXCP_74xx:
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excp_model = "PowerPC 74xx";
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break;
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case POWERPC_EXCP_BOOKE:
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excp_model = "PowerPC BookE";
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break;
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#if defined(TARGET_PPC64)
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case POWERPC_EXCP_970:
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excp_model = "PowerPC 970";
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break;
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#endif
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default:
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excp_model = "Unknown or invalid";
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break;
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}
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switch (env->bus_model) {
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case PPC_FLAGS_INPUT_6xx:
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bus_model = "PowerPC 6xx";
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break;
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case PPC_FLAGS_INPUT_BookE:
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bus_model = "PowerPC BookE";
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break;
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case PPC_FLAGS_INPUT_405:
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bus_model = "PowerPC 405";
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break;
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case PPC_FLAGS_INPUT_401:
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bus_model = "PowerPC 401/403";
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break;
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case PPC_FLAGS_INPUT_RCPU:
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bus_model = "RCPU / MPC8xx";
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break;
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#if defined(TARGET_PPC64)
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case PPC_FLAGS_INPUT_970:
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bus_model = "PowerPC 970";
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break;
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#endif
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default:
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bus_model = "Unknown or invalid";
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break;
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}
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printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
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" MMU model : %s\n",
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object_class_get_name(OBJECT_CLASS(pcc)),
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pcc->pvr, pcc->msr_mask, mmu_model);
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#if !defined(CONFIG_USER_ONLY)
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if (env->tlb.tlb6) {
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printf(" %d %s TLB in %d ways\n",
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env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
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env->nb_ways);
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}
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#endif
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printf(" Exceptions model : %s\n"
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" Bus model : %s\n",
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excp_model, bus_model);
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printf(" MSR features :\n");
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if (env->flags & POWERPC_FLAG_SPE) {
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printf(" signal processing engine enable"
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"\n");
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} else if (env->flags & POWERPC_FLAG_VRE) {
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printf(" vector processor enable\n");
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}
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if (env->flags & POWERPC_FLAG_TGPR) {
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printf(" temporary GPRs\n");
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} else if (env->flags & POWERPC_FLAG_CE) {
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printf(" critical input enable\n");
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}
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if (env->flags & POWERPC_FLAG_SE) {
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printf(" single-step trace mode\n");
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} else if (env->flags & POWERPC_FLAG_DWE) {
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printf(" debug wait enable\n");
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} else if (env->flags & POWERPC_FLAG_UBLE) {
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printf(" user BTB lock enable\n");
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}
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if (env->flags & POWERPC_FLAG_BE) {
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printf(" branch-step trace mode\n");
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} else if (env->flags & POWERPC_FLAG_DE) {
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printf(" debug interrupt enable\n");
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}
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if (env->flags & POWERPC_FLAG_PX) {
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printf(" inclusive protection\n");
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} else if (env->flags & POWERPC_FLAG_PMM) {
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printf(" performance monitor mark\n");
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}
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if (env->flags == POWERPC_FLAG_NONE) {
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printf(" none\n");
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}
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printf(" Time-base/decrementer clock source: %s\n",
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env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
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dump_ppc_insns(env);
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dump_ppc_sprs(env);
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fflush(stdout);
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}
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#endif
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return;
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unrealize:
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@ -218,8 +218,6 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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/* translate.c */
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/* #define PPC_DUMP_CPU */
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int ppc_fixup_cpu(PowerPCCPU *cpu);
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void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp);
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void destroy_ppc_opcodes(PowerPCCPU *cpu);
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@ -216,9 +216,6 @@ struct opc_handler_t {
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uint64_t type2;
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/* handler */
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void (*handler)(DisasContext *ctx);
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#if defined(PPC_DUMP_CPU)
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const char *oname;
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#endif
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};
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/* SPR load/store helpers */
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@ -8463,10 +8460,6 @@ static int register_direct_insn(opc_handler_t **ppc_opcodes,
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if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
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printf("*** ERROR: opcode %02x already assigned in main "
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"opcode table\n", idx);
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#if defined(PPC_DUMP_CPU)
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printf(" Registered handler '%s' - new handler '%s'\n",
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ppc_opcodes[idx]->oname, handler->oname);
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#endif
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return -1;
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}
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@ -8487,10 +8480,6 @@ static int register_ind_in_table(opc_handler_t **table,
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if (!is_indirect_opcode(table[idx1])) {
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printf("*** ERROR: idx %02x already assigned to a direct "
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"opcode\n", idx1);
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#if defined(PPC_DUMP_CPU)
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printf(" Registered handler '%s' - new handler '%s'\n",
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ind_table(table[idx1])[idx2]->oname, handler->oname);
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#endif
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return -1;
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}
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}
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@ -8498,10 +8487,6 @@ static int register_ind_in_table(opc_handler_t **table,
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insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
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printf("*** ERROR: opcode %02x already assigned in "
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"opcode table %02x\n", idx2, idx1);
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#if defined(PPC_DUMP_CPU)
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printf(" Registered handler '%s' - new handler '%s'\n",
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ind_table(table[idx1])[idx2]->oname, handler->oname);
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#endif
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return -1;
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}
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@ -8683,96 +8668,6 @@ void destroy_ppc_opcodes(PowerPCCPU *cpu)
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}
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}
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#if defined(PPC_DUMP_CPU)
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static void dump_ppc_insns(CPUPPCState *env)
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{
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opc_handler_t **table, *handler;
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const char *p, *q;
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uint8_t opc1, opc2, opc3, opc4;
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printf("Instructions set:\n");
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/* opc1 is 6 bits long */
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for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
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table = env->opcodes;
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handler = table[opc1];
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if (is_indirect_opcode(handler)) {
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/* opc2 is 5 bits long */
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for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
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table = env->opcodes;
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handler = env->opcodes[opc1];
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table = ind_table(handler);
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handler = table[opc2];
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if (is_indirect_opcode(handler)) {
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table = ind_table(handler);
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/* opc3 is 5 bits long */
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for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
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opc3++) {
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handler = table[opc3];
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if (is_indirect_opcode(handler)) {
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table = ind_table(handler);
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/* opc4 is 5 bits long */
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for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
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opc4++) {
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handler = table[opc4];
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if (handler->handler != &gen_invalid) {
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printf("INSN: %02x %02x %02x %02x -- "
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"(%02d %04d %02d) : %s\n",
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opc1, opc2, opc3, opc4,
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opc1, (opc3 << 5) | opc2, opc4,
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handler->oname);
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}
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}
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} else {
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if (handler->handler != &gen_invalid) {
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/* Special hack to properly dump SPE insns */
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p = strchr(handler->oname, '_');
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if (p == NULL) {
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printf("INSN: %02x %02x %02x (%02d %04d) : "
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"%s\n",
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opc1, opc2, opc3, opc1,
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(opc3 << 5) | opc2,
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handler->oname);
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} else {
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q = "speundef";
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if ((p - handler->oname) != strlen(q)
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|| (memcmp(handler->oname, q, strlen(q))
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!= 0)) {
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/* First instruction */
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printf("INSN: %02x %02x %02x"
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"(%02d %04d) : %.*s\n",
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opc1, opc2 << 1, opc3, opc1,
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(opc3 << 6) | (opc2 << 1),
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(int)(p - handler->oname),
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handler->oname);
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}
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if (strcmp(p + 1, q) != 0) {
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/* Second instruction */
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printf("INSN: %02x %02x %02x "
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"(%02d %04d) : %s\n", opc1,
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(opc2 << 1) | 1, opc3, opc1,
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(opc3 << 6) | (opc2 << 1) | 1,
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p + 1);
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}
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}
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}
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}
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}
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} else {
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if (handler->handler != &gen_invalid) {
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printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
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opc1, opc2, opc1, opc2, handler->oname);
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}
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}
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}
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} else {
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if (handler->handler != &gen_invalid) {
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printf("INSN: %02x -- -- (%02d ----) : %s\n",
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opc1, opc1, handler->oname);
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}
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}
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}
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}
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#endif
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int ppc_fixup_cpu(PowerPCCPU *cpu)
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{
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CPUPPCState *env = &cpu->env;
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