sh7750: convert cache and tlb to memory API
Signed-off-by: Benoit Canet <benoit.canet@gmail.com> Signed-off-by: Avi Kivity <avi@redhat.com>
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382863e2c6
commit
1a4004c772
43
hw/sh7750.c
43
hw/sh7750.c
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@ -42,6 +42,7 @@ typedef struct SH7750State {
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MemoryRegion iomem_ff8;
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MemoryRegion iomem_1fc;
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MemoryRegion iomem_ffc;
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MemoryRegion mmct_iomem;
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/* CPU */
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CPUSH4State *cpu;
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/* Peripheral frequency in Hz */
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@ -623,18 +624,23 @@ static struct intc_group groups_irl[] = {
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#define MM_UTLB_DATA (7)
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#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
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static uint32_t invalid_read(void *opaque, target_phys_addr_t addr)
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static uint64_t invalid_read(void *opaque, target_phys_addr_t addr)
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{
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abort();
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return 0;
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}
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static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
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static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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SH7750State *s = opaque;
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uint32_t ret = 0;
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if (size != 4) {
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return invalid_read(opaque, addr);
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}
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switch (MM_REGION_TYPE(addr)) {
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case MM_ICACHE_ADDR:
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case MM_ICACHE_DATA:
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@ -664,16 +670,20 @@ static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
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}
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static void invalid_write(void *opaque, target_phys_addr_t addr,
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uint32_t mem_value)
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uint64_t mem_value)
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{
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abort();
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}
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static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
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uint32_t mem_value)
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static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr,
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uint64_t mem_value, unsigned size)
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{
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SH7750State *s = opaque;
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if (size != 4) {
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invalid_write(opaque, addr, mem_value);
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}
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switch (MM_REGION_TYPE(addr)) {
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case MM_ICACHE_ADDR:
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case MM_ICACHE_DATA:
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@ -702,22 +712,15 @@ static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
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}
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}
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static CPUReadMemoryFunc * const sh7750_mmct_read[] = {
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invalid_read,
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invalid_read,
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sh7750_mmct_readl
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};
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static CPUWriteMemoryFunc * const sh7750_mmct_write[] = {
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invalid_write,
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invalid_write,
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sh7750_mmct_writel
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static const struct MemoryRegionOps sh7750_mmct_ops = {
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.read = sh7750_mmct_read,
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.write = sh7750_mmct_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
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{
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SH7750State *s;
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int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
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s = g_malloc0(sizeof(SH7750State));
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s->cpu = cpu;
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@ -749,11 +752,9 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
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&s->iomem, 0x1fc00000, 0x1000);
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memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
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sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read,
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sh7750_mmct_write, s,
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DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(0xf0000000, 0x08000000,
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sh7750_mm_cache_and_tlb);
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memory_region_init_io(&s->mmct_iomem, &sh7750_mmct_ops, s,
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"cache-and-tlb", 0x08000000);
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memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
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sh_intc_init(&s->intc, NR_SOURCES,
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_INTC_ARRAY(mask_registers),
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