target/ppc: Split out ppc_hash64_xlate
Mirror the interface of ppc_radix64_xlate, putting all of the logic for hash64 translation into a single function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210621125115.67717-6-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -873,8 +873,10 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
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return -1;
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}
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int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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MMUAccessType access_type, int mmu_idx)
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static bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr,
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MMUAccessType access_type,
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hwaddr *raddrp, int *psizep, int *protp,
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bool guest_visible)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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@ -918,9 +920,11 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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slb = &vrma_slbe;
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if (build_vrma_slbe(cpu, slb) != 0) {
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/* Invalid VRMA setup, machine check */
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if (guest_visible) {
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cs->exception_index = POWERPC_EXCP_MCHECK;
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env->error_code = 0;
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return 1;
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}
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return false;
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}
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goto skip_slb_search;
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@ -929,6 +933,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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/* Emulated old-style RMO mode, bounds check against RMLS */
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if (raddr >= limit) {
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if (!guest_visible) {
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return false;
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}
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switch (access_type) {
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case MMU_INST_FETCH:
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ppc_hash64_set_isi(cs, SRR1_PROTFAULT);
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@ -943,15 +950,16 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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default:
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g_assert_not_reached();
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}
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return 1;
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return false;
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}
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raddr |= env->spr[SPR_RMOR];
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}
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tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
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TARGET_PAGE_SIZE);
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return 0;
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*raddrp = raddr;
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*protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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*psizep = TARGET_PAGE_BITS;
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return true;
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}
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/* 2. Translation is on, so look up the SLB */
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@ -964,6 +972,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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exit(1);
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}
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/* Segment still not found, generate the appropriate interrupt */
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if (!guest_visible) {
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return false;
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}
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switch (access_type) {
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case MMU_INST_FETCH:
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cs->exception_index = POWERPC_EXCP_ISEG;
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@ -978,20 +989,25 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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default:
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g_assert_not_reached();
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}
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return 1;
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return false;
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}
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skip_slb_search:
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/* 3. Check for segment level no-execute violation */
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if (access_type == MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) {
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if (guest_visible) {
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ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD);
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return 1;
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}
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return false;
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}
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/* 4. Locate the PTE in the hash table */
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ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
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if (ptex == -1) {
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if (!guest_visible) {
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return false;
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}
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switch (access_type) {
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case MMU_INST_FETCH:
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ppc_hash64_set_isi(cs, SRR1_NOPTE);
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@ -1005,7 +1021,7 @@ skip_slb_search:
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default:
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g_assert_not_reached();
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}
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return 1;
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return false;
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}
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qemu_log_mask(CPU_LOG_MMU,
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"found PTE at index %08" HWADDR_PRIx "\n", ptex);
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@ -1021,6 +1037,9 @@ skip_slb_search:
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if (need_prot & ~prot) {
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/* Access right violation */
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qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
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if (!guest_visible) {
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return false;
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}
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if (access_type == MMU_INST_FETCH) {
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int srr1 = 0;
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if (PAGE_EXEC & ~exec_prot) {
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@ -1045,7 +1064,7 @@ skip_slb_search:
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}
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ppc_hash64_set_dsi(cs, eaddr, dsisr);
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}
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return 1;
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return false;
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}
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qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
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@ -1069,66 +1088,40 @@ skip_slb_search:
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/* 7. Determine the real address from the PTE */
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raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
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*raddrp = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
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*protp = prot;
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*psizep = apshift;
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return true;
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}
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int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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MMUAccessType access_type, int mmu_idx)
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{
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CPUState *cs = CPU(cpu);
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int page_size, prot;
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hwaddr raddr;
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if (!ppc_hash64_xlate(cpu, eaddr, access_type, &raddr,
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&page_size, &prot, true)) {
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return 1;
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}
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tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
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prot, mmu_idx, 1ULL << apshift);
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prot, mmu_idx, 1UL << page_size);
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return 0;
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}
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hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
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hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
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{
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CPUPPCState *env = &cpu->env;
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ppc_slb_t vrma_slbe;
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ppc_slb_t *slb;
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hwaddr ptex, raddr;
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ppc_hash_pte64_t pte;
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unsigned apshift;
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int psize, prot;
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hwaddr raddr;
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/* Handle real mode */
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if (msr_dr == 0) {
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/* In real mode the top 4 effective address bits are ignored */
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raddr = addr & 0x0FFFFFFFFFFFFFFFULL;
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if (cpu->vhyp) {
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/*
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* In virtual hypervisor mode, there's nothing to do:
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* EA == GPA == qemu guest address
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*/
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return raddr;
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} else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) {
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/* In HV mode, add HRMOR if top EA bit is clear */
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return raddr | env->spr[SPR_HRMOR];
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} else if (ppc_hash64_use_vrma(env)) {
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/* Emulated VRMA mode */
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slb = &vrma_slbe;
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if (build_vrma_slbe(cpu, slb) != 0) {
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return -1;
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}
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} else {
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target_ulong limit = rmls_limit(cpu);
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/* Emulated old-style RMO mode, bounds check against RMLS */
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if (raddr >= limit) {
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return -1;
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}
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return raddr | env->spr[SPR_RMOR];
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}
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} else {
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slb = slb_lookup(cpu, addr);
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if (!slb) {
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return -1;
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}
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}
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ptex = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift);
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if (ptex == -1) {
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if (!ppc_hash64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr,
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&psize, &prot, false)) {
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return -1;
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}
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return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
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& TARGET_PAGE_MASK;
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return raddr & TARGET_PAGE_MASK;
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}
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void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
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