OMAP DMA input signals must be level-triggered.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3096 c046a42c-6fe2-441c-8c8c-71466251a162
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cfa0b71dd8
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24
hw/omap.c
24
hw/omap.c
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@ -403,6 +403,7 @@ struct omap_dma_s {
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target_phys_addr_t base;
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omap_clk clk;
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int64_t delay;
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uint32_t drq;
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uint16_t gcr;
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int run_count;
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@ -511,7 +512,7 @@ next_channel:
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if (request > 0)
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s->ch[channel].status |= 0x40; /* External request */
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if (s->delay)
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if (s->delay && !qemu_timer_pending(s->tm))
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qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
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if (request > 0) {
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@ -593,7 +594,8 @@ static void omap_dma_channel_run(struct omap_dma_s *s)
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if (s->ch[ch].interrupts & 0x08)
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s->ch[ch].status |= 0x08;
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if (s->ch[ch].sync && s->ch[ch].fs) {
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if (s->ch[ch].sync && s->ch[ch].fs &&
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!(s->drq & (1 << s->ch[ch].sync))) {
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s->ch[ch].status &= ~0x40;
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omap_dma_request_stop(s, ch);
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}
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@ -607,7 +609,8 @@ static void omap_dma_channel_run(struct omap_dma_s *s)
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if (s->ch[ch].interrupts & 0x04)
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s->ch[ch].status |= 0x04;
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if (s->ch[ch].sync && !s->ch[ch].fs) {
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if (s->ch[ch].sync && !s->ch[ch].fs &&
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!(s->drq & (1 << s->ch[ch].sync))) {
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s->ch[ch].status &= ~0x40;
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omap_dma_request_stop(s, ch);
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}
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@ -750,7 +753,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
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s->ch[ch].running = 1;
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omap_dma_channel_load(s, ch);
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}
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if (!s->ch[ch].sync)
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if (!s->ch[ch].sync || (s->drq & (1 << s->ch[ch].sync)))
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omap_dma_request_run(s, ch, 0);
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} else {
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s->ch[ch].running = 0;
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@ -949,9 +952,14 @@ static CPUWriteMemoryFunc *omap_dma_writefn[] = {
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static void omap_dma_request(void *opaque, int drq, int req)
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{
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struct omap_dma_s *s = (struct omap_dma_s *) opaque;
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/* All the request pins are edge triggered. */
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if (req)
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omap_dma_request_run(s, 0, drq);
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/* The request pins are level triggered. */
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if (req) {
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if (~s->drq & (1 << drq)) {
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s->drq |= 1 << drq;
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omap_dma_request_run(s, 0, drq);
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}
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} else
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s->drq &= ~(1 << drq);
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}
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static void omap_dma_clk_update(void *opaque, int line, int on)
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@ -974,6 +982,7 @@ static void omap_dma_reset(struct omap_dma_s *s)
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qemu_del_timer(s->tm);
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s->gcr = 0x0004;
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s->drq = 0x00000000;
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s->run_count = 0;
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s->lcd_ch.src = emiff;
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s->lcd_ch.condition = 0;
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@ -1002,6 +1011,7 @@ struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
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omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
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mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
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omap_dma_reset(s);
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omap_dma_clk_update(s, 0, 1);
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iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
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omap_dma_writefn, s);
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