target/mips: Clean up handling of CP0 register 0
Clean up handling of CP0 register 0. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-2-git-send-email-aleksandar.markovic@rt-rk.com>
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@ -277,6 +277,9 @@ typedef struct mips_def_t mips_def_t;
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/* CP0 Register 00 */
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#define CP0_REG00__INDEX 0
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#define CP0_REG00__MVPCONTROL 1
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#define CP0_REG00__MVPCONF0 2
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#define CP0_REG00__MVPCONF1 3
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#define CP0_REG00__VPCONTROL 4
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/* CP0 Register 01 */
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/* CP0 Register 02 */
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@ -6813,26 +6813,26 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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switch (reg) {
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case CP0_REGISTER_00:
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switch (sel) {
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case 0:
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case CP0_REG00__INDEX:
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
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register_name = "Index";
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break;
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case 1:
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case CP0_REG00__MVPCONTROL:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_mvpcontrol(arg, cpu_env);
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register_name = "MVPControl";
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break;
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case 2:
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case CP0_REG00__MVPCONF0:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_mvpconf0(arg, cpu_env);
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register_name = "MVPConf0";
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break;
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case 3:
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case CP0_REG00__MVPCONF1:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_mvpconf1(arg, cpu_env);
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register_name = "MVPConf1";
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break;
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case 4:
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case CP0_REG00__VPCONTROL:
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CP0_CHECK(ctx->vp);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
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register_name = "VPControl";
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@ -7573,26 +7573,26 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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switch (reg) {
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case CP0_REGISTER_00:
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switch (sel) {
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case 0:
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case CP0_REG00__INDEX:
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gen_helper_mtc0_index(cpu_env, arg);
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register_name = "Index";
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break;
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case 1:
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case CP0_REG00__MVPCONTROL:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_mvpcontrol(cpu_env, arg);
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register_name = "MVPControl";
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break;
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case 2:
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case CP0_REG00__MVPCONF0:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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/* ignored */
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register_name = "MVPConf0";
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break;
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case 3:
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case CP0_REG00__MVPCONF1:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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/* ignored */
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register_name = "MVPConf1";
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break;
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case 4:
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case CP0_REG00__VPCONTROL:
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CP0_CHECK(ctx->vp);
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/* ignored */
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register_name = "VPControl";
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@ -8319,26 +8319,26 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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switch (reg) {
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case CP0_REGISTER_00:
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switch (sel) {
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case 0:
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case CP0_REG00__INDEX:
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
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register_name = "Index";
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break;
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case 1:
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case CP0_REG00__MVPCONTROL:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_mvpcontrol(arg, cpu_env);
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register_name = "MVPControl";
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break;
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case 2:
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case CP0_REG00__MVPCONF0:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_mvpconf0(arg, cpu_env);
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register_name = "MVPConf0";
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break;
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case 3:
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case CP0_REG00__MVPCONF1:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_mvpconf1(arg, cpu_env);
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register_name = "MVPConf1";
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break;
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case 4:
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case CP0_REG00__VPCONTROL:
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CP0_CHECK(ctx->vp);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
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register_name = "VPControl";
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@ -9033,26 +9033,26 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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switch (reg) {
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case CP0_REGISTER_00:
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switch (sel) {
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case 0:
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case CP0_REG00__INDEX:
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gen_helper_mtc0_index(cpu_env, arg);
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register_name = "Index";
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break;
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case 1:
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case CP0_REG00__MVPCONTROL:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_mvpcontrol(cpu_env, arg);
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register_name = "MVPControl";
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break;
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case 2:
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case CP0_REG00__MVPCONF0:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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/* ignored */
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register_name = "MVPConf0";
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break;
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case 3:
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case CP0_REG00__MVPCONF1:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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/* ignored */
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register_name = "MVPConf1";
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break;
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case 4:
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case CP0_REG00__VPCONTROL:
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CP0_CHECK(ctx->vp);
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/* ignored */
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register_name = "VPControl";
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