target/i386: Pass in port to gen_check_io
Pass in a pre-truncated TCGv_i32 value. We were doing the truncation of EDX in multiple places, now only once per insn. While all callers use s->tmp2_i32, for cleanliness of the subroutine, use a parameter anyway. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-48-richard.henderson@linaro.org>
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@ -674,19 +674,23 @@ static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n)
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}
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}
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static bool gen_check_io(DisasContext *s, MemOp ot, uint32_t svm_flags)
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/*
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* Validate that access to [port, port + 1<<ot) is allowed.
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* Raise #GP, or VMM exit if not.
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*/
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static bool gen_check_io(DisasContext *s, MemOp ot, TCGv_i32 port,
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uint32_t svm_flags)
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{
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tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
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if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) {
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switch (ot) {
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case MO_8:
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gen_helper_check_iob(cpu_env, s->tmp2_i32);
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gen_helper_check_iob(cpu_env, port);
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break;
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case MO_16:
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gen_helper_check_iow(cpu_env, s->tmp2_i32);
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gen_helper_check_iow(cpu_env, port);
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break;
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case MO_32:
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gen_helper_check_iol(cpu_env, s->tmp2_i32);
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gen_helper_check_iol(cpu_env, port);
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break;
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default:
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tcg_abort();
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@ -702,7 +706,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, uint32_t svm_flags)
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svm_flags |= SVM_IOIO_REP_MASK;
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}
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svm_flags |= 1 << (SVM_IOIO_SIZE_SHIFT + ot);
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gen_helper_svm_check_io(cpu_env, s->tmp2_i32,
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gen_helper_svm_check_io(cpu_env, port,
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tcg_constant_i32(svm_flags),
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tcg_constant_i32(next_eip - cur_eip));
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}
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@ -6479,8 +6483,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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case 0x6c: /* insS */
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case 0x6d:
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ot = mo_b_d32(b, dflag);
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tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]);
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if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) {
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tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
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tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
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if (!gen_check_io(s, ot, s->tmp2_i32,
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SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) {
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break;
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}
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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@ -6499,8 +6505,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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case 0x6e: /* outsS */
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case 0x6f:
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ot = mo_b_d32(b, dflag);
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tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]);
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if (!gen_check_io(s, ot, SVM_IOIO_STR_MASK)) {
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tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
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tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
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if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_STR_MASK)) {
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break;
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}
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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@ -6524,14 +6531,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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case 0xe5:
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ot = mo_b_d32(b, dflag);
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val = x86_ldub_code(env, s);
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tcg_gen_movi_tl(s->T0, val);
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if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK)) {
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tcg_gen_movi_i32(s->tmp2_i32, val);
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if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) {
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break;
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}
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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tcg_gen_movi_i32(s->tmp2_i32, val);
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gen_helper_in_func(ot, s->T1, s->tmp2_i32);
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gen_op_mov_reg_v(s, ot, R_EAX, s->T1);
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gen_bpt_io(s, s->tmp2_i32, ot);
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@ -6543,16 +6549,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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case 0xe7:
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ot = mo_b_d32(b, dflag);
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val = x86_ldub_code(env, s);
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tcg_gen_movi_tl(s->T0, val);
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if (!gen_check_io(s, ot, 0)) {
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tcg_gen_movi_i32(s->tmp2_i32, val);
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if (!gen_check_io(s, ot, s->tmp2_i32, 0)) {
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break;
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}
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gen_op_mov_v_reg(s, ot, s->T1, R_EAX);
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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tcg_gen_movi_i32(s->tmp2_i32, val);
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gen_op_mov_v_reg(s, ot, s->T1, R_EAX);
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tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
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gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32);
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gen_bpt_io(s, s->tmp2_i32, ot);
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@ -6563,14 +6567,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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case 0xec:
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case 0xed:
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ot = mo_b_d32(b, dflag);
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tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]);
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if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK)) {
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tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
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tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
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if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) {
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break;
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}
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
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gen_helper_in_func(ot, s->T1, s->tmp2_i32);
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gen_op_mov_reg_v(s, ot, R_EAX, s->T1);
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gen_bpt_io(s, s->tmp2_i32, ot);
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@ -6581,16 +6585,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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case 0xee:
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case 0xef:
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ot = mo_b_d32(b, dflag);
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tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]);
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if (!gen_check_io(s, ot, 0)) {
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tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]);
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tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32);
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if (!gen_check_io(s, ot, s->tmp2_i32, 0)) {
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break;
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}
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gen_op_mov_v_reg(s, ot, s->T1, R_EAX);
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
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gen_op_mov_v_reg(s, ot, s->T1, R_EAX);
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tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
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gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32);
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gen_bpt_io(s, s->tmp2_i32, ot);
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