target/arm: Honor the HCR_EL2.TPCP bit
This bit traps EL1 access to cache maintenance insns that operate to the point of coherency or persistence. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -4314,6 +4314,28 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
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return CP_ACCESS_OK;
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}
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static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
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const ARMCPRegInfo *ri,
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bool isread)
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{
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/* Cache invalidate/clean to Point of Coherency or Persistence... */
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switch (arm_current_el(env)) {
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case 0:
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/* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
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if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
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return CP_ACCESS_TRAP;
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}
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/* fall through */
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case 1:
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/* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
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if (arm_hcr_el2_eff(env) & HCR_TPCP) {
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return CP_ACCESS_TRAP_EL2;
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}
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break;
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}
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return CP_ACCESS_OK;
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}
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/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
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* Page D4-1736 (DDI0487A.b)
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*/
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@ -4721,14 +4743,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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.accessfn = aa64_cacheop_access },
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{ .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
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.access = PL1_W, .type = ARM_CP_NOP },
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.access = PL1_W, .accessfn = aa64_cacheop_poc_access,
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.type = ARM_CP_NOP },
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{ .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
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.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
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{ .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
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.access = PL0_W, .type = ARM_CP_NOP,
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.accessfn = aa64_cacheop_access },
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.accessfn = aa64_cacheop_poc_access },
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{ .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
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.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
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@ -4739,7 +4762,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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{ .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
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.access = PL0_W, .type = ARM_CP_NOP,
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.accessfn = aa64_cacheop_access },
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.accessfn = aa64_cacheop_poc_access },
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{ .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
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.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
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@ -4921,17 +4944,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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{ .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
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.type = ARM_CP_NOP, .access = PL1_W },
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{ .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
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.type = ARM_CP_NOP, .access = PL1_W },
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.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
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{ .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
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.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
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{ .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
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.type = ARM_CP_NOP, .access = PL1_W },
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.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
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{ .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
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.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
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{ .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
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.type = ARM_CP_NOP, .access = PL1_W },
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{ .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
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.type = ARM_CP_NOP, .access = PL1_W },
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.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
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{ .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
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.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
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/* MMU Domain access control / MPU write buffer control */
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@ -6750,7 +6773,7 @@ static const ARMCPRegInfo dcpop_reg[] = {
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{ .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
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.access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
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.accessfn = aa64_cacheop_access, .writefn = dccvap_writefn },
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.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
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REGINFO_SENTINEL
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};
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@ -6758,7 +6781,7 @@ static const ARMCPRegInfo dcpodp_reg[] = {
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{ .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
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.access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
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.accessfn = aa64_cacheop_access, .writefn = dccvap_writefn },
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.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
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REGINFO_SENTINEL
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};
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#endif /*CONFIG_USER_ONLY*/
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