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qemu-patch-raspberry4
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Let address_space_rw() calls pass a boolean 'is_write' argument 

Since its introduction in commit ac1970fbe8, address_space_rw()
takes a boolean 'is_write' argument. Fix the codebase by using
an explicit boolean type.

This commit was produced with the included Coccinelle script
scripts/coccinelle/exec_rw_const.

Inspired-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
stable-5.0
Philippe Mathieu-Daudé 2020-02-19 20:14:26 +01:00
parent ae5883abec
commit 1ccda935d4
7 changed files with 41 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
exec.c
View File

@ -3815,8 +3815,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr,
attrs, buf, l);
} else {
address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
attrs, buf, l, 0);
address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, attrs, buf,
l, false);
}
len -= l;
buf += l;

27
hw/net/dp8393x.c
View File

@ -276,7 +276,7 @@ static void dp8393x_do_load_cam(dp8393xState *s)
while (s->regs[SONIC_CDC] & 0x1f) {
/* Fill current entry */
address_space_rw(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
MEMTXATTRS_UNSPECIFIED, s->data, size, false);
s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
@ -294,7 +294,7 @@ static void dp8393x_do_load_cam(dp8393xState *s)
/* Read CAM enable */
address_space_rw(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
MEMTXATTRS_UNSPECIFIED, s->data, size, false);
s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
@ -312,7 +312,7 @@ static void dp8393x_do_read_rra(dp8393xState *s)
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
size = sizeof(uint16_t) * 4 * width;
address_space_rw(&s->as, dp8393x_rrp(s),
MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
MEMTXATTRS_UNSPECIFIED, s->data, size, false);
/* Update SONIC registers */
s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
@ -427,7 +427,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
MEMTXATTRS_UNSPECIFIED, s->data, size, false);
tx_len = 0;
/* Update registers */
@ -452,7 +452,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
len = sizeof(s->tx_buffer) - tx_len;
}
address_space_rw(&s->as, dp8393x_tsa(s),
MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0);
MEMTXATTRS_UNSPECIFIED,
&s->tx_buffer[tx_len], len, false);
tx_len += len;
i++;
@ -461,7 +462,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
size = sizeof(uint16_t) * 3 * width;
address_space_rw(&s->as,
dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width,
MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
MEMTXATTRS_UNSPECIFIED, s->data, size, false);
s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
@ -496,7 +497,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
size = sizeof(uint16_t) * width;
address_space_rw(&s->as,
dp8393x_ttda(s),
MEMTXATTRS_UNSPECIFIED, s->data, size, 1);
MEMTXATTRS_UNSPECIFIED, s->data, size, true);
if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
/* Read footer of packet */
@ -505,7 +506,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
dp8393x_ttda(s) +
sizeof(uint16_t) *
(4 + 3 * s->regs[SONIC_TFC]) * width,
MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
MEMTXATTRS_UNSPECIFIED, s->data, size, false);
s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1;
if (dp8393x_get(s, width, 0) & 0x1) {
/* EOL detected */
@ -768,7 +769,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
size = sizeof(uint16_t) * 1 * width;
address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
s->data, size, 0);
s->data, size, false);
if (dp8393x_get(s, width, 0) & 0x1) {
/* Still EOL ; stop reception */
return -1;
@ -790,7 +791,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, buf, rx_len);
address += rx_len;
address_space_rw(&s->as, address,
MEMTXATTRS_UNSPECIFIED, &checksum, 4, 1);
MEMTXATTRS_UNSPECIFIED, &checksum, 4, true);
rx_len += 4;
s->regs[SONIC_CRBA1] = address >> 16;
s->regs[SONIC_CRBA0] = address & 0xffff;
@ -819,12 +820,12 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */
size = sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, dp8393x_crda(s),
MEMTXATTRS_UNSPECIFIED, s->data, size, 1);
MEMTXATTRS_UNSPECIFIED, s->data, size, true);
/* Move to next descriptor */
size = sizeof(uint16_t) * width;
address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
MEMTXATTRS_UNSPECIFIED, s->data, size, false);
s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
if (s->regs[SONIC_LLFA] & 0x1) {
/* EOL detected */
@ -838,7 +839,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
}
s->data[0] = 0;
address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED,
s->data, sizeof(uint16_t), 1);
s->data, sizeof(uint16_t), true);
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);

11
hw/net/i82596.c
View File

@ -149,7 +149,7 @@ static void i82596_transmit(I82596State *s, uint32_t addr)
if (s->nic && len) {
assert(len <= sizeof(s->tx_buffer));
address_space_rw(&address_space_memory, tba,
MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len, 0);
MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len, false);
DBG(PRINT_PKTHDR("Send", &s->tx_buffer));
DBG(printf("Sending %d bytes\n", len));
qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, len);
@ -173,7 +173,7 @@ static void set_individual_address(I82596State *s, uint32_t addr)
nc = qemu_get_queue(s->nic);
m = s->conf.macaddr.a;
address_space_rw(&address_space_memory, addr + 8,
MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN, 0);
MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN, false);
qemu_format_nic_info_str(nc, m);
trace_i82596_new_mac(nc->info_str);
}
@ -192,7 +192,7 @@ static void set_multicast_list(I82596State *s, uint32_t addr)
uint8_t multicast_addr[ETH_ALEN];
address_space_rw(&address_space_memory,
addr + i * ETH_ALEN, MEMTXATTRS_UNSPECIFIED,
multicast_addr, ETH_ALEN, 0);
multicast_addr, ETH_ALEN, false);
DBG(printf("Add multicast entry " MAC_FMT "\n",
MAC_ARG(multicast_addr)));
unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) &
@ -261,7 +261,8 @@ static void command_loop(I82596State *s)
byte_cnt = MIN(byte_cnt, sizeof(s->config));
/* copy byte_cnt max. */
address_space_rw(&address_space_memory, s->cmd_p + 8,
MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt, 0);
MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt,
false);
/* config byte according to page 35ff */
s->config[2] &= 0x82; /* mask valid bits */
s->config[2] |= 0x40;
@ -647,7 +648,7 @@ ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t sz)
len -= num;
if (len == 0) { /* copy crc */
address_space_rw(&address_space_memory, rba - 4,
MEMTXATTRS_UNSPECIFIED, crc_ptr, 4, 1);
MEMTXATTRS_UNSPECIFIED, crc_ptr, 4, true);
}
num |= 0x4000; /* set F BIT */

4
hw/net/lasi_i82596.c
View File

@ -55,8 +55,8 @@ static void lasi_82596_mem_write(void *opaque, hwaddr addr,
* Provided for SeaBIOS only. Write MAC of Network card to addr @val.
* Needed for the PDC_LAN_STATION_ID_READ PDC call.
*/
address_space_rw(&address_space_memory, val,
MEMTXATTRS_UNSPECIFIED, d->state.conf.macaddr.a, ETH_ALEN, 1);
address_space_rw(&address_space_memory, val, MEMTXATTRS_UNSPECIFIED,
d->state.conf.macaddr.a, ETH_ALEN, true);
break;
}
}

12
scripts/coccinelle/exec_rw_const.cocci
View File

@ -9,6 +9,18 @@
--dir .
*/
// Convert to boolean
@@
expression E1, E2, E3, E4, E5;
@@
(
- address_space_rw(E1, E2, E3, E4, E5, 0)
+ address_space_rw(E1, E2, E3, E4, E5, false)
|
- address_space_rw(E1, E2, E3, E4, E5, 1)
+ address_space_rw(E1, E2, E3, E4, E5, true)
)
// Use address_space_write instead of casting to non-const
@@
type T;

2
target/i386/hvf/vmx.h
View File

@ -128,7 +128,7 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0)
address_space_rw(&address_space_memory,
rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
MEMTXATTRS_UNSPECIFIED,
pdpte, 32, 0);
pdpte, 32, false);
/* Only set PDPTE when appropriate. */
for (i = 0; i < 4; i++) {
wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);

8
target/i386/hvf/x86_mmu.c
View File

@ -89,7 +89,7 @@ static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt,
index = gpt_entry(pt->gva, level, pae);
address_space_rw(&address_space_memory, gpa + index * pte_size(pae),
MEMTXATTRS_UNSPECIFIED, &pte, pte_size(pae), 0);
MEMTXATTRS_UNSPECIFIED, &pte, pte_size(pae), false);
pt->pte[level - 1] = pte;
@ -238,8 +238,8 @@ void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int bytes
if (!mmu_gva_to_gpa(cpu, gva, &gpa)) {
VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva);
} else {
address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED,
data, copy, 1);
address_space_rw(&address_space_memory, gpa,
MEMTXATTRS_UNSPECIFIED, data, copy, true);
}
bytes -= copy;
@ -260,7 +260,7 @@ void vmx_read_mem(struct CPUState *cpu, void *data, target_ulong gva, int bytes)
VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva);
}
address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED,
data, copy, 0);
data, copy, false);
bytes -= copy;
gva += copy;