haraldwolff/qemu-patch-raspberry4
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

A Single RISC-V Patch for 4.0-rc0

Browse source 
There was a regression introduced by the decodetree conversion that has
 a fairly straight-forward fix.  Since this fixes bugs that everyone has
 hit I'd like to target it for rc0.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAlyPK+8THHBhbG1lckBk
 YWJiZWx0LmNvbQAKCRDvTKFQLMurQYCED/4lfpNWcH6t+qfOKLn8NuOPXwlFfKZC
 GJccWfcCj87gDo5xhhV0+bUtdfw54y+PG8YENvpYSpF2c9S0SRUWzHZdDpOt0Fg+
 LH0nTMx5Mnx1+XYtExtAfJ9mN61ekpNobeBS9fr4idHUSH/pLa3kMuB9+bW+yw+U
 fNSm/OJyDyiAaG+aDlfJqgJ34G7Q7ZfAJYK2Db3reAt2jxXud/D/fjypv3MYU1R3
 XedYZqVsCvnrFdQIHo2hEuvNbLoMgyGVluHs49b5CYTE0qpY/BUtgPIkhOBFC1j0
 SEPuC9iHkNz/uWAnj841454I6xXCDybI9daycoMDV4rQYQo0IzSOokdDIWh5fTpC
 zT4sOktGUg5OKmgnvifb61cjVRe6G7BQjCN1nFfNQv+DFY5VYtcI3u1M7AUYzp3h
 PfiBBybffwn9Gl7K9go0RDpHqTrkT9N5DrXvPAP2a7nmgX7yyBp61/+3QsRMaE0/
 wozAHgUIKu9U4kHlB6ACi5KHfzYwH2GAoPbcEFdyZ1i6I3NKM7Y1yQgv2PZJ0O8S
 M0CBFckc05Sd3elhxT0ri4vqXua5AKAdWCe7+jrtdzxGEeWhmmHsYgcKUFVQE5Je
 ob9qERa9iQG8mMjPe5YajeAN3x+epOY7Vd2fr/sFgWNJyRT27B43qWoUDccgye/U
 7N/hVmCbILuAVA==
 =raRT
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-4.0-rc0' into staging

A Single RISC-V Patch for 4.0-rc0

There was a regression introduced by the decodetree conversion that has
a fairly straight-forward fix.  Since this fixes bugs that everyone has
hit I'd like to target it for rc0.

# gpg: Signature made Mon 18 Mar 2019 05:26:07 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-4.0-rc0:
  target/riscv: Fix manually parsed 16 bit insn

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-03-18 09:52:37 +00:00
parent d4e65539e5 f330433b36
commit 1d023a5296
1 changed files with 25 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

30
target/riscv/insn_trans/trans_rvc.inc.c
View file

@ -44,10 +44,19 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
{
#ifdef TARGET_RISCV32
/* C.FLW ( RV32FC-only ) */
return false;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
arg_c_lw tmp;
decode_insn16_extract_cl_w(&tmp, ctx->opcode);
arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
return trans_flw(ctx, &arg);
#else
/* C.LD ( RV64C/RV128C-only ) */
return false;
arg_c_fld tmp;
decode_insn16_extract_cl_d(&tmp, ctx->opcode);
arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
return trans_ld(ctx, &arg);
#endif
}
@ -67,10 +76,19 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
{
#ifdef TARGET_RISCV32
/* C.FSW ( RV32FC-only ) */
return false;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
arg_c_sw tmp;
decode_insn16_extract_cs_w(&tmp, ctx->opcode);
arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
return trans_fsw(ctx, &arg);
#else
/* C.SD ( RV64C/RV128C-only ) */
return false;
arg_c_fsd tmp;
decode_insn16_extract_cs_d(&tmp, ctx->opcode);
arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
return trans_sd(ctx, &arg);
#endif
}
@ -88,7 +106,9 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
{
#ifdef TARGET_RISCV32
/* C.JAL */
arg_jal arg = { .rd = 1, .imm = a->imm };
arg_c_j tmp;
decode_insn16_extract_cj(&tmp, ctx->opcode);
arg_jal arg = { .rd = 1, .imm = tmp.imm };
return trans_jal(ctx, &arg);
#else
/* C.ADDIW */