target/arm: Use gvec for VSHR, VSHL
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181011205206.3552-13-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -6373,8 +6373,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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size--;
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}
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shift = (insn >> 16) & ((1 << (3 + size)) - 1);
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/* To avoid excessive duplication of ops we implement shift
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by immediate using the variable shift operations. */
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if (op < 8) {
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/* Shift by immediate:
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VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
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@ -6386,37 +6384,62 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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}
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/* Right shifts are encoded as N - shift, where N is the
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element size in bits. */
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if (op <= 4)
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if (op <= 4) {
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shift = shift - (1 << (size + 3));
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}
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switch (op) {
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case 0: /* VSHR */
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/* Right shift comes here negative. */
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shift = -shift;
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/* Shifts larger than the element size are architecturally
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* valid. Unsigned results in all zeros; signed results
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* in all sign bits.
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*/
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if (!u) {
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tcg_gen_gvec_sari(size, rd_ofs, rm_ofs,
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MIN(shift, (8 << size) - 1),
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vec_size, vec_size);
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} else if (shift >= 8 << size) {
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tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
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} else {
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tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
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vec_size, vec_size);
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}
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return 0;
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case 5: /* VSHL, VSLI */
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if (!u) { /* VSHL */
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/* Shifts larger than the element size are
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* architecturally valid and results in zero.
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*/
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if (shift >= 8 << size) {
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tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
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} else {
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tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
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vec_size, vec_size);
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}
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return 0;
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}
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break;
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}
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if (size == 3) {
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count = q + 1;
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} else {
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count = q ? 4: 2;
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}
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switch (size) {
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case 0:
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imm = (uint8_t) shift;
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imm |= imm << 8;
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imm |= imm << 16;
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break;
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case 1:
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imm = (uint16_t) shift;
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imm |= imm << 16;
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break;
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case 2:
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case 3:
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imm = shift;
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break;
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default:
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abort();
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}
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/* To avoid excessive duplication of ops we implement shift
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* by immediate using the variable shift operations.
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*/
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imm = dup_const(size, shift);
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for (pass = 0; pass < count; pass++) {
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if (size == 3) {
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neon_load_reg64(cpu_V0, rm + pass);
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tcg_gen_movi_i64(cpu_V1, imm);
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switch (op) {
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case 0: /* VSHR */
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case 1: /* VSRA */
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if (u)
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gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
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@ -6447,6 +6470,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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cpu_V0, cpu_V1);
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}
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break;
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default:
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g_assert_not_reached();
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}
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if (op == 1 || op == 3) {
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/* Accumulate. */
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@ -6475,7 +6500,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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tmp2 = tcg_temp_new_i32();
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tcg_gen_movi_i32(tmp2, imm);
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switch (op) {
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case 0: /* VSHR */
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case 1: /* VSRA */
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GEN_NEON_INTEGER_OP(shl);
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break;
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@ -6513,6 +6537,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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case 7: /* VQSHL */
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GEN_NEON_INTEGER_OP_ENV(qshl);
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break;
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default:
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g_assert_not_reached();
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}
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tcg_temp_free_i32(tmp2);
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