target/riscv: Only flush TLB if SATP.ASID changes
There is an analogous change for ARM here: https://patchwork.kernel.org/patch/10649857 Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -723,7 +723,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
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if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
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if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
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return -1;
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return -1;
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} else {
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} else {
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if((val ^ env->satp) & SATP_ASID) {
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tlb_flush(CPU(riscv_env_get_cpu(env)));
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tlb_flush(CPU(riscv_env_get_cpu(env)));
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}
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env->satp = val;
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env->satp = val;
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}
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}
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}
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}
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