hw/intc/arm_gicv3: Introduce redist-region-count array property
To prepare for multiple redistributor regions, we introduce an array of uint32_t properties that stores the redistributor count of each redistributor region. Non accelerated VGICv3 only supports a single redistributor region. The capacity of all redist regions is checked against the number of vcpus. Machvirt is updated to set those properties, ie. a single redistributor region with count set to the number of vcpus capped by 123. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-4-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -523,6 +523,15 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
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if (!kvm_irqchip_in_kernel()) {
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if (!kvm_irqchip_in_kernel()) {
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qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
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qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
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}
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}
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if (type == 3) {
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uint32_t redist0_capacity =
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vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
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uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
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qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
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qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
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}
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qdev_init_nofail(gicdev);
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qdev_init_nofail(gicdev);
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gicbusdev = SYS_BUS_DEVICE(gicdev);
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gicbusdev = SYS_BUS_DEVICE(gicdev);
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sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
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sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
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@ -1322,7 +1331,7 @@ static void machvirt_init(MachineState *machine)
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* many redistributors we can fit into the memory map.
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* many redistributors we can fit into the memory map.
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*/
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*/
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if (vms->gic_version == 3) {
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if (vms->gic_version == 3) {
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virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000;
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virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
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} else {
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} else {
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virt_max_cpus = GIC_NCPU;
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virt_max_cpus = GIC_NCPU;
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}
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}
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@ -373,7 +373,17 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
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return;
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return;
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}
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}
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gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
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if (s->nb_redist_regions != 1) {
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error_setg(errp, "VGICv3 redist region number(%d) not equal to 1",
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s->nb_redist_regions);
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return;
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}
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gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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gicv3_init_cpuif(s);
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gicv3_init_cpuif(s);
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}
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}
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@ -247,11 +247,22 @@ static const VMStateDescription vmstate_gicv3 = {
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};
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};
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void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
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void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
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const MemoryRegionOps *ops)
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const MemoryRegionOps *ops, Error **errp)
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{
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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int rdist_capacity = 0;
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int i;
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int i;
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for (i = 0; i < s->nb_redist_regions; i++) {
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rdist_capacity += s->redist_region_count[i];
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}
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if (rdist_capacity < s->num_cpu) {
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error_setg(errp, "Capacity of the redist regions(%d) "
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"is less than number of vcpus(%d)",
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rdist_capacity, s->num_cpu);
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return;
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}
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/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
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/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
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* GPIO array layout is thus:
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* GPIO array layout is thus:
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* [0..N-1] spi
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* [0..N-1] spi
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@ -277,11 +288,18 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
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memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
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memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
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"gicv3_dist", 0x10000);
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"gicv3_dist", 0x10000);
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memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s,
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"gicv3_redist", 0x20000 * s->num_cpu);
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sysbus_init_mmio(sbd, &s->iomem_dist);
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sysbus_init_mmio(sbd, &s->iomem_dist);
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sysbus_init_mmio(sbd, &s->iomem_redist);
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s->iomem_redist = g_new0(MemoryRegion, s->nb_redist_regions);
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for (i = 0; i < s->nb_redist_regions; i++) {
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char *name = g_strdup_printf("gicv3_redist_region[%d]", i);
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memory_region_init_io(&s->iomem_redist[i], OBJECT(s),
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ops ? &ops[1] : NULL, s, name,
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s->redist_region_count[i] * GICV3_REDIST_SIZE);
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sysbus_init_mmio(sbd, &s->iomem_redist[i]);
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g_free(name);
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}
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}
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}
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static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
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static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
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@ -363,6 +381,13 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
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}
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}
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}
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}
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static void arm_gicv3_finalize(Object *obj)
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{
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GICv3State *s = ARM_GICV3_COMMON(obj);
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g_free(s->redist_region_count);
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}
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static void arm_gicv3_common_reset(DeviceState *dev)
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static void arm_gicv3_common_reset(DeviceState *dev)
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{
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{
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GICv3State *s = ARM_GICV3_COMMON(dev);
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GICv3State *s = ARM_GICV3_COMMON(dev);
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@ -467,6 +492,8 @@ static Property arm_gicv3_common_properties[] = {
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DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
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DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
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DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
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DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
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DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
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DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
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DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
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redist_region_count, qdev_prop_uint32, uint32_t),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -488,6 +515,7 @@ static const TypeInfo arm_gicv3_common_type = {
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.instance_size = sizeof(GICv3State),
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.instance_size = sizeof(GICv3State),
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.class_size = sizeof(ARMGICv3CommonClass),
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.class_size = sizeof(ARMGICv3CommonClass),
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.class_init = arm_gicv3_common_class_init,
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.class_init = arm_gicv3_common_class_init,
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.instance_finalize = arm_gicv3_finalize,
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.abstract = true,
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.abstract = true,
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.interfaces = (InterfaceInfo []) {
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.interfaces = (InterfaceInfo []) {
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{ TYPE_ARM_LINUX_BOOT_IF },
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{ TYPE_ARM_LINUX_BOOT_IF },
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@ -784,7 +784,11 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
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return;
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return;
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}
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}
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gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
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gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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for (i = 0; i < s->num_cpu; i++) {
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for (i = 0; i < s->num_cpu; i++) {
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ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
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ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
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@ -808,7 +812,8 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
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kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
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kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
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KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);
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KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);
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kvm_arm_register_device(&s->iomem_redist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
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kvm_arm_register_device(&s->iomem_redist[0], -1,
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KVM_DEV_ARM_VGIC_GRP_ADDR,
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KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
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KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
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if (kvm_has_gsi_routing()) {
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if (kvm_has_gsi_routing()) {
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@ -35,6 +35,8 @@
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#define GICV3_MAXIRQ 1020
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#define GICV3_MAXIRQ 1020
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#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
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#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
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#define GICV3_REDIST_SIZE 0x20000
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/* Number of SGI target-list bits */
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/* Number of SGI target-list bits */
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#define GICV3_TARGETLIST_BITS 16
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#define GICV3_TARGETLIST_BITS 16
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@ -210,7 +212,9 @@ struct GICv3State {
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/*< public >*/
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/*< public >*/
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MemoryRegion iomem_dist; /* Distributor */
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MemoryRegion iomem_dist; /* Distributor */
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MemoryRegion iomem_redist; /* Redistributors */
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MemoryRegion *iomem_redist; /* Redistributor Regions */
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uint32_t *redist_region_count; /* redistributor count within each region */
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uint32_t nb_redist_regions; /* number of redist regions */
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uint32_t num_cpu;
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uint32_t num_cpu;
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uint32_t num_irq;
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uint32_t num_irq;
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@ -292,6 +296,6 @@ typedef struct ARMGICv3CommonClass {
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} ARMGICv3CommonClass;
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} ARMGICv3CommonClass;
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void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
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void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
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const MemoryRegionOps *ops);
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const MemoryRegionOps *ops, Error **errp);
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#endif
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#endif
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