intel_iommu: define several structs for IOMMU IR
Several data structs are defined to better support the rest of the patches: IRTE to parse remapping table entries, and IOAPIC/MSI related structure bits to parse interrupt entries to be filled in by guest kernel. Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -52,6 +52,8 @@ typedef struct IntelIOMMUState IntelIOMMUState;
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typedef struct VTDAddressSpace VTDAddressSpace;
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typedef struct VTDIOTLBEntry VTDIOTLBEntry;
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typedef struct VTDBus VTDBus;
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typedef union VTD_IRTE VTD_IRTE;
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typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
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/* Context-Entry */
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struct VTDContextEntry {
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@ -90,6 +92,78 @@ struct VTDIOTLBEntry {
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bool write_flags;
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};
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/* Interrupt Remapping Table Entry Definition */
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union VTD_IRTE {
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struct {
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#ifdef HOST_WORDS_BIGENDIAN
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uint32_t dest_id:32; /* Destination ID */
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uint32_t __reserved_1:8; /* Reserved 1 */
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uint32_t vector:8; /* Interrupt Vector */
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uint32_t irte_mode:1; /* IRTE Mode */
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uint32_t __reserved_0:3; /* Reserved 0 */
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uint32_t __avail:4; /* Available spaces for software */
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uint32_t delivery_mode:3; /* Delivery Mode */
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uint32_t trigger_mode:1; /* Trigger Mode */
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uint32_t redir_hint:1; /* Redirection Hint */
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uint32_t dest_mode:1; /* Destination Mode */
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uint32_t fault_disable:1; /* Fault Processing Disable */
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uint32_t present:1; /* Whether entry present/available */
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#else
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uint32_t present:1; /* Whether entry present/available */
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uint32_t fault_disable:1; /* Fault Processing Disable */
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uint32_t dest_mode:1; /* Destination Mode */
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uint32_t redir_hint:1; /* Redirection Hint */
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uint32_t trigger_mode:1; /* Trigger Mode */
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uint32_t delivery_mode:3; /* Delivery Mode */
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uint32_t __avail:4; /* Available spaces for software */
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uint32_t __reserved_0:3; /* Reserved 0 */
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uint32_t irte_mode:1; /* IRTE Mode */
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uint32_t vector:8; /* Interrupt Vector */
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uint32_t __reserved_1:8; /* Reserved 1 */
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uint32_t dest_id:32; /* Destination ID */
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#endif
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uint16_t source_id:16; /* Source-ID */
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#ifdef HOST_WORDS_BIGENDIAN
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uint64_t __reserved_2:44; /* Reserved 2 */
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uint64_t sid_vtype:2; /* Source-ID Validation Type */
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uint64_t sid_q:2; /* Source-ID Qualifier */
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#else
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uint64_t sid_q:2; /* Source-ID Qualifier */
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uint64_t sid_vtype:2; /* Source-ID Validation Type */
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uint64_t __reserved_2:44; /* Reserved 2 */
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#endif
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} QEMU_PACKED;
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uint64_t data[2];
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};
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#define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */
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#define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */
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/* Programming format for MSI/MSI-X addresses */
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union VTD_IR_MSIAddress {
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struct {
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#ifdef HOST_WORDS_BIGENDIAN
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uint32_t __head:12; /* Should always be: 0x0fee */
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uint32_t index_l:15; /* Interrupt index bit 14-0 */
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uint32_t int_mode:1; /* Interrupt format */
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uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
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uint32_t index_h:1; /* Interrupt index bit 15 */
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uint32_t __not_care:2;
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#else
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uint32_t __not_care:2;
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uint32_t index_h:1; /* Interrupt index bit 15 */
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uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
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uint32_t int_mode:1; /* Interrupt format */
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uint32_t index_l:15; /* Interrupt index bit 14-0 */
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uint32_t __head:12; /* Should always be: 0x0fee */
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#endif
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} QEMU_PACKED;
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uint32_t data;
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};
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/* When IR is enabled, all MSI/MSI-X data bits should be zero */
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#define VTD_IR_MSI_DATA (0)
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/* The iommu (DMAR) device state struct */
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struct IntelIOMMUState {
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X86IOMMUState x86_iommu;
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