tcg-aarch64: Support muluh, mulsh
Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com> Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
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@ -311,6 +311,8 @@ typedef enum {
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I3508_LSRV = 0x1ac02400,
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I3508_LSRV = 0x1ac02400,
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I3508_ASRV = 0x1ac02800,
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I3508_ASRV = 0x1ac02800,
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I3508_RORV = 0x1ac02c00,
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I3508_RORV = 0x1ac02c00,
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I3508_SMULH = 0x9b407c00,
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I3508_UMULH = 0x9bc07c00,
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/* Logical shifted register instructions (without a shift). */
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/* Logical shifted register instructions (without a shift). */
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I3510_AND = 0x0a000000,
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I3510_AND = 0x0a000000,
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@ -1565,6 +1567,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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args[5], const_args[4], const_args[5], true);
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args[5], const_args[4], const_args[5], true);
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break;
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break;
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case INDEX_op_muluh_i64:
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tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2);
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break;
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case INDEX_op_mulsh_i64:
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tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
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break;
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case INDEX_op_mov_i64:
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case INDEX_op_mov_i64:
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case INDEX_op_mov_i32:
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case INDEX_op_mov_i32:
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case INDEX_op_movi_i64:
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case INDEX_op_movi_i64:
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@ -1694,6 +1703,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
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{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },
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{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },
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{ INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
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{ INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
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{ INDEX_op_muluh_i64, { "r", "r", "r" } },
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{ INDEX_op_mulsh_i64, { "r", "r", "r" } },
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{ -1 },
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{ -1 },
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};
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};
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@ -89,8 +89,8 @@ typedef enum {
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 0
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#define TCG_TARGET_HAS_mulu2_i64 0
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#define TCG_TARGET_HAS_muls2_i64 0
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#define TCG_TARGET_HAS_muls2_i64 0
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#define TCG_TARGET_HAS_muluh_i64 0
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#define TCG_TARGET_HAS_muluh_i64 1
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#define TCG_TARGET_HAS_mulsh_i64 0
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#define TCG_TARGET_HAS_mulsh_i64 1
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enum {
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enum {
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TCG_AREG0 = TCG_REG_X19,
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TCG_AREG0 = TCG_REG_X19,
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