tcg-sparc: Mask shift immediates to avoid illegal insns.
The xtensa-test image generates a sra_i32 with count 0x40. Whether this is accident of tcg constant propagation or originating directly from the instruction stream is immaterial. Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -1154,13 +1154,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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goto gen_arith;
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goto gen_arith;
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case INDEX_op_shl_i32:
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case INDEX_op_shl_i32:
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c = SHIFT_SLL;
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c = SHIFT_SLL;
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goto gen_arith;
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do_shift32:
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/* Limit immediate shift count lest we create an illegal insn. */
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tcg_out_arithc(s, args[0], args[1], args[2] & 31, const_args[2], c);
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break;
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case INDEX_op_shr_i32:
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case INDEX_op_shr_i32:
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c = SHIFT_SRL;
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c = SHIFT_SRL;
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goto gen_arith;
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goto do_shift32;
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case INDEX_op_sar_i32:
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case INDEX_op_sar_i32:
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c = SHIFT_SRA;
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c = SHIFT_SRA;
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goto gen_arith;
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goto do_shift32;
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case INDEX_op_mul_i32:
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case INDEX_op_mul_i32:
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c = ARITH_UMUL;
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c = ARITH_UMUL;
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goto gen_arith;
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goto gen_arith;
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@ -1281,13 +1284,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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break;
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break;
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case INDEX_op_shl_i64:
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case INDEX_op_shl_i64:
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c = SHIFT_SLLX;
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c = SHIFT_SLLX;
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goto gen_arith;
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do_shift64:
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/* Limit immediate shift count lest we create an illegal insn. */
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tcg_out_arithc(s, args[0], args[1], args[2] & 63, const_args[2], c);
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break;
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case INDEX_op_shr_i64:
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case INDEX_op_shr_i64:
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c = SHIFT_SRLX;
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c = SHIFT_SRLX;
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goto gen_arith;
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goto do_shift64;
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case INDEX_op_sar_i64:
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case INDEX_op_sar_i64:
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c = SHIFT_SRAX;
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c = SHIFT_SRAX;
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goto gen_arith;
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goto do_shift64;
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case INDEX_op_mul_i64:
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case INDEX_op_mul_i64:
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c = ARITH_MULX;
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c = ARITH_MULX;
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goto gen_arith;
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goto gen_arith;
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