target-xtensa: tests: pre-process tests linker script
Xtensa cores have configurable interrupt vectors and endiannes. This information is needed to link executable images correctly for a specific core configuration. Instead of hard-coding dc232 defaults pull endianness, number of high-priority interrupts and location of vectors from the core configuration and pass it through the C preprocessor. While at it clean up tabs and align the initial stack on 16 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov
parent
dec71d2d63
commit
20303e42d4
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@ -13,6 +13,7 @@ SIMFLAGS = --xtensa-core=DC_B_232L --exit_with_target_code $(EXTFLAGS)
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SIMDEBUG = --gdbserve=0
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endif
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HOST_CC = gcc
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CC = $(CROSS)gcc
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AS = $(CROSS)gcc -x assembler-with-cpp
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LD = $(CROSS)ld
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@ -21,7 +22,7 @@ XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa
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INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target-xtensa/core-$(CORE)
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XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS))
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LDFLAGS = -T$(XTENSA_SRC_PATH)/linker.ld
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LDFLAGS = -Tlinker.ld
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CRT = crt.o vectors.o
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@ -59,13 +60,16 @@ TESTCASES += test_windowed.tst
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all: build
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linker.ld: $(XTENSA_SRC_PATH)/linker.ld.S
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$(HOST_CC) $(XTENSA_INC) -E -P $< -o $@
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%.o: $(XTENSA_SRC_PATH)/%.c
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$(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@
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%.o: $(XTENSA_SRC_PATH)/%.S
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$(CC) $(XTENSA_INC) $(ASFLAGS) -c $< -o $@
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%.tst: %.o $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
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%.tst: %.o linker.ld $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
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$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@
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build: $(TESTCASES)
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@ -85,4 +89,4 @@ host-debug-%.tst: %.tst
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gdb --args $(SIM) $(SIMFLAGS) ./$<
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clean:
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$(RM) -fr $(TESTCASES) $(CRT)
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$(RM) -fr $(TESTCASES) $(CRT) linker.ld
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@ -1,112 +0,0 @@
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OUTPUT_FORMAT("elf32-xtensa-le")
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ENTRY(_start)
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__DYNAMIC = 0;
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MEMORY {
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ram : ORIGIN = 0xd0000000, LENGTH = 0x08000000 /* 128M */
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rom : ORIGIN = 0xfe000000, LENGTH = 0x00001000 /* 4k */
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}
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SECTIONS
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{
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.init :
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{
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*(.init)
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*(.init.*)
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} > rom
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.vector :
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{
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. = 0x00000000;
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*(.vector.window_overflow_4)
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*(.vector.window_overflow_4.*)
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. = 0x00000040;
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*(.vector.window_underflow_4)
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*(.vector.window_underflow_4.*)
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. = 0x00000080;
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*(.vector.window_overflow_8)
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*(.vector.window_overflow_8.*)
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. = 0x000000c0;
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*(.vector.window_underflow_8)
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*(.vector.window_underflow_8.*)
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. = 0x00000100;
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*(.vector.window_overflow_12)
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*(.vector.window_overflow_12.*)
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. = 0x00000140;
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*(.vector.window_underflow_12)
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*(.vector.window_underflow_12.*)
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. = 0x00000180;
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*(.vector.level2)
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*(.vector.level2.*)
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. = 0x000001c0;
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*(.vector.level3)
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*(.vector.level3.*)
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. = 0x00000200;
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*(.vector.level4)
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*(.vector.level4.*)
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. = 0x00000240;
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*(.vector.level5)
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*(.vector.level5.*)
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. = 0x00000280;
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*(.vector.level6)
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*(.vector.level6.*)
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. = 0x000002c0;
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*(.vector.level7)
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*(.vector.level7.*)
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. = 0x00000300;
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*(.vector.kernel)
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*(.vector.kernel.*)
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. = 0x00000340;
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*(.vector.user)
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*(.vector.user.*)
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. = 0x000003c0;
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*(.vector.double)
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*(.vector.double.*)
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} > ram
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.text :
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{
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_ftext = .;
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*(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*)
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_etext = .;
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} > ram
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.rodata :
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{
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. = ALIGN(4);
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_frodata = .;
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*(.rodata .rodata.* .gnu.linkonce.r.*)
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*(.rodata1)
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_erodata = .;
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} > ram
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.data :
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{
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. = ALIGN(4);
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_fdata = .;
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*(.data .data.* .gnu.linkonce.d.*)
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*(.data1)
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_gp = ALIGN(16);
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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_edata = .;
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} > ram
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.bss :
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{
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. = ALIGN(4);
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_fbss = .;
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*(.dynsbss)
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*(.sbss .sbss.* .gnu.linkonce.sb.*)
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*(.scommon)
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*(.dynbss)
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*(.bss .bss.* .gnu.linkonce.b.*)
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*(COMMON)
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_ebss = .;
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_end = .;
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} > ram
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}
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PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);
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130
tests/tcg/xtensa/linker.ld.S
Normal file
130
tests/tcg/xtensa/linker.ld.S
Normal file
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@ -0,0 +1,130 @@
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#include <core-isa.h>
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#if XTENSA_HAVE_BE
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OUTPUT_FORMAT("elf32-xtensa-be")
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#else
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OUTPUT_FORMAT("elf32-xtensa-le")
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#endif
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ENTRY(_start)
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__DYNAMIC = 0;
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MEMORY {
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ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = 0x08000000 /* 128M */
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rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = 0x00001000 /* 4k */
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}
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SECTIONS
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{
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.init :
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{
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*(.init)
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*(.init.*)
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} > rom
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.vector :
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{
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. = XCHAL_WINDOW_OF4_VECOFS;
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*(.vector.window_overflow_4)
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*(.vector.window_overflow_4.*)
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. = XCHAL_WINDOW_UF4_VECOFS;
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*(.vector.window_underflow_4)
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*(.vector.window_underflow_4.*)
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. = XCHAL_WINDOW_OF8_VECOFS;
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*(.vector.window_overflow_8)
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*(.vector.window_overflow_8.*)
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. = XCHAL_WINDOW_UF8_VECOFS;
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*(.vector.window_underflow_8)
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*(.vector.window_underflow_8.*)
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. = XCHAL_WINDOW_OF12_VECOFS;
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*(.vector.window_overflow_12)
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*(.vector.window_overflow_12.*)
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. = XCHAL_WINDOW_UF12_VECOFS;
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*(.vector.window_underflow_12)
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*(.vector.window_underflow_12.*)
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
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. = XCHAL_INTLEVEL2_VECOFS;
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*(.vector.level2)
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*(.vector.level2.*)
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#endif
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
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. = XCHAL_INTLEVEL3_VECOFS;
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*(.vector.level3)
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*(.vector.level3.*)
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#endif
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
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. = XCHAL_INTLEVEL4_VECOFS;
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*(.vector.level4)
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*(.vector.level4.*)
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#endif
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
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. = XCHAL_INTLEVEL5_VECOFS;
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*(.vector.level5)
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*(.vector.level5.*)
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#endif
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
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. = XCHAL_INTLEVEL6_VECOFS;
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*(.vector.level6)
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*(.vector.level6.*)
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#endif
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
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. = XCHAL_INTLEVEL7_VECOFS;
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*(.vector.level7)
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*(.vector.level7.*)
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#endif
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. = XCHAL_KERNEL_VECOFS;
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*(.vector.kernel)
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*(.vector.kernel.*)
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. = XCHAL_USER_VECOFS;
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*(.vector.user)
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*(.vector.user.*)
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. = XCHAL_DOUBLEEXC_VECOFS;
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*(.vector.double)
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*(.vector.double.*)
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} > ram
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.text :
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{
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_ftext = .;
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*(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*)
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_etext = .;
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} > ram
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.rodata :
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{
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. = ALIGN(4);
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_frodata = .;
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*(.rodata .rodata.* .gnu.linkonce.r.*)
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*(.rodata1)
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_erodata = .;
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} > ram
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.data :
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{
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. = ALIGN(4);
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_fdata = .;
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*(.data .data.* .gnu.linkonce.d.*)
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*(.data1)
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_gp = ALIGN(16);
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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_edata = .;
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} > ram
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.bss :
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{
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. = ALIGN(4);
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_fbss = .;
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*(.dynsbss)
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*(.sbss .sbss.* .gnu.linkonce.sb.*)
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*(.scommon)
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*(.dynbss)
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*(.bss .bss.* .gnu.linkonce.b.*)
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*(COMMON)
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_ebss = .;
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_end = .;
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} > ram
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}
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PROVIDE(_fstack = (ORIGIN(ram) & 0xf0000000) + LENGTH(ram) - 16);
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