target/ppc: Implement the rest of gen_ld_atomic
These cases were stubbed out. For now, implement them only within a serial context, forcing parallel execution to synchronize. It would be possible to implement these with cmpxchg loops, if we care. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -3078,16 +3078,45 @@ LARX(lbarx, DEF_MEMOP(MO_UB))
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LARX(lharx, DEF_MEMOP(MO_UW))
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LARX(lwarx, DEF_MEMOP(MO_UL))
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static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,
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TCGv EA, TCGCond cond, int addend)
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{
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TCGv t = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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TCGv u = tcg_temp_new();
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tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
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tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
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tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
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tcg_gen_addi_tl(u, t, addend);
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/* E.g. for fetch and increment bounded... */
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/* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
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tcg_gen_movcond_tl(cond, u, t, t2, u, t);
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tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
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/* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
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tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
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tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
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tcg_temp_free(t);
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tcg_temp_free(t2);
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tcg_temp_free(u);
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}
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static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
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{
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uint32_t gpr_FC = FC(ctx->opcode);
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TCGv EA = tcg_temp_new();
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int rt = rD(ctx->opcode);
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bool need_serial;
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TCGv src, dst;
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gen_addr_register(ctx, EA);
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dst = cpu_gpr[rD(ctx->opcode)];
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src = cpu_gpr[rD(ctx->opcode) + 1];
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dst = cpu_gpr[rt];
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src = cpu_gpr[(rt + 1) & 31];
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need_serial = false;
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memop |= MO_ALIGN;
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switch (gpr_FC) {
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case 0: /* Fetch and add */
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@ -3117,17 +3146,63 @@ static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
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case 8: /* Swap */
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tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
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break;
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case 16: /* compare and swap not equal */
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case 24: /* Fetch and increment bounded */
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case 25: /* Fetch and increment equal */
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case 28: /* Fetch and decrement bounded */
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gen_invalid(ctx);
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case 16: /* Compare and swap not equal */
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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need_serial = true;
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} else {
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
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if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
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tcg_gen_mov_tl(t1, src);
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} else {
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tcg_gen_ext32u_tl(t1, src);
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}
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tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
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cpu_gpr[(rt + 2) & 31], t0);
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tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
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tcg_gen_mov_tl(dst, t0);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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break;
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case 24: /* Fetch and increment bounded */
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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need_serial = true;
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} else {
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gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
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}
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break;
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case 25: /* Fetch and increment equal */
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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need_serial = true;
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} else {
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gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
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}
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break;
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case 28: /* Fetch and decrement bounded */
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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need_serial = true;
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} else {
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gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
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}
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break;
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default:
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/* invoke data storage error handler */
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gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
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}
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tcg_temp_free(EA);
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if (need_serial) {
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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}
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static void gen_lwat(DisasContext *ctx)
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