e1000: Cosmetic and alignment fixes
This fixes some alignment and cosmetic issues. The changes are made in order that the following patches in this series will look like integral parts of the code surrounding them, while conforming to the coding style. Although some changes in unrelated areas are also made. Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com> Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
parent
ecc804cac3
commit
20f3e86362
166
hw/net/e1000.c
166
hw/net/e1000.c
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@ -41,20 +41,20 @@
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#ifdef E1000_DEBUG
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#ifdef E1000_DEBUG
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enum {
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enum {
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DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
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DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
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DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
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DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
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DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
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DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
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DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET,
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DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET,
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};
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};
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#define DBGBIT(x) (1<<DEBUG_##x)
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#define DBGBIT(x) (1<<DEBUG_##x)
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static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
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static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
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#define DBGOUT(what, fmt, ...) do { \
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#define DBGOUT(what, fmt, ...) do { \
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if (debugflags & DBGBIT(what)) \
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if (debugflags & DBGBIT(what)) \
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fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
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fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
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} while (0)
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} while (0)
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#else
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#else
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#define DBGOUT(what, fmt, ...) do {} while (0)
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#define DBGOUT(what, fmt, ...) do {} while (0)
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#endif
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#endif
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#define IOPORT_SIZE 0x40
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#define IOPORT_SIZE 0x40
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@ -118,7 +118,7 @@ typedef struct E1000State_st {
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} tx;
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} tx;
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struct {
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struct {
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uint32_t val_in; // shifted in from guest driver
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uint32_t val_in; /* shifted in from guest driver */
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uint16_t bitnum_in;
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uint16_t bitnum_in;
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uint16_t bitnum_out;
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uint16_t bitnum_out;
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uint16_t reading;
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uint16_t reading;
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@ -155,19 +155,19 @@ typedef struct E1000BaseClass {
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#define E1000_DEVICE_GET_CLASS(obj) \
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#define E1000_DEVICE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(E1000BaseClass, (obj), TYPE_E1000_BASE)
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OBJECT_GET_CLASS(E1000BaseClass, (obj), TYPE_E1000_BASE)
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#define defreg(x) x = (E1000_##x>>2)
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#define defreg(x) x = (E1000_##x>>2)
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enum {
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enum {
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defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
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defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
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defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
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defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
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defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
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defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
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defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
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defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
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defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
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defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
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defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
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defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
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defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
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defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
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defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
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defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
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defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
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defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
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defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
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defreg(RA), defreg(MTA), defreg(CRCERRS), defreg(VFTA),
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defreg(VET), defreg(RDTR), defreg(RADV), defreg(TADV),
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defreg(VET), defreg(RDTR), defreg(RADV), defreg(TADV),
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defreg(ITR),
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defreg(ITR),
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};
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};
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@ -226,18 +226,18 @@ enum { NPHYWRITEOPS = ARRAY_SIZE(phyreg_writeops) };
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enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
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enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
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static const char phy_regcap[0x20] = {
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static const char phy_regcap[0x20] = {
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[PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
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[PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
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[PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
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[PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
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[PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
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[PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
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[PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
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[PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
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[PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
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[PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
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[PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R,
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[PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R,
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[PHY_AUTONEG_EXP] = PHY_R,
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[PHY_AUTONEG_EXP] = PHY_R,
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};
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};
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/* PHY_ID2 documented in 8254x_GBe_SDM.pdf, pp. 250 */
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/* PHY_ID2 documented in 8254x_GBe_SDM.pdf, pp. 250 */
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static const uint16_t phy_reg_init[] = {
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static const uint16_t phy_reg_init[] = {
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[PHY_CTRL] = MII_CR_SPEED_SELECT_MSB |
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[PHY_CTRL] = MII_CR_SPEED_SELECT_MSB |
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MII_CR_FULL_DUPLEX |
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MII_CR_FULL_DUPLEX |
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MII_CR_AUTO_NEG_EN,
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MII_CR_AUTO_NEG_EN,
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@ -264,15 +264,15 @@ static const uint16_t phy_reg_init[] = {
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};
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};
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static const uint32_t mac_reg_init[] = {
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static const uint32_t mac_reg_init[] = {
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[PBA] = 0x00100030,
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[PBA] = 0x00100030,
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[LEDCTL] = 0x602,
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[LEDCTL] = 0x602,
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[CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
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[CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
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E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
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E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
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[STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
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[STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
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E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
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E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
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E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
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E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
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E1000_STATUS_LU,
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E1000_STATUS_LU,
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[MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
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[MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
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E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
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E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
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E1000_MANC_RMCP_EN,
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E1000_MANC_RMCP_EN,
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};
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};
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@ -510,17 +510,19 @@ set_eecd(E1000State *s, int index, uint32_t val)
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s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
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s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
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E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
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E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
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if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
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if (!(E1000_EECD_CS & val)) { /* CS inactive; nothing to do */
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return;
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if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
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s->eecd_state.val_in = 0;
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s->eecd_state.bitnum_in = 0;
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s->eecd_state.bitnum_out = 0;
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s->eecd_state.reading = 0;
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}
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if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
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return;
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return;
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if (!(E1000_EECD_SK & val)) { // falling edge
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}
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if (E1000_EECD_CS & (val ^ oldval)) { /* CS rise edge; reset state */
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s->eecd_state.val_in = 0;
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s->eecd_state.bitnum_in = 0;
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s->eecd_state.bitnum_out = 0;
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s->eecd_state.reading = 0;
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}
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if (!(E1000_EECD_SK & (val ^ oldval))) { /* no clock edge */
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return;
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}
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if (!(E1000_EECD_SK & val)) { /* falling edge */
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s->eecd_state.bitnum_out++;
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s->eecd_state.bitnum_out++;
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return;
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return;
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}
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}
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@ -621,12 +623,13 @@ xmit_seg(E1000State *s)
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css = tp->ipcss;
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css = tp->ipcss;
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DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
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DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
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frames, tp->size, css);
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frames, tp->size, css);
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if (tp->ip) { // IPv4
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if (tp->ip) { /* IPv4 */
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stw_be_p(tp->data+css+2, tp->size - css);
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stw_be_p(tp->data+css+2, tp->size - css);
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stw_be_p(tp->data+css+4,
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stw_be_p(tp->data+css+4,
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be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
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be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
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} else // IPv6
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} else { /* IPv6 */
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stw_be_p(tp->data+css+4, tp->size - css);
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stw_be_p(tp->data+css+4, tp->size - css);
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}
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css = tp->tucss;
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css = tp->tucss;
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len = tp->size - css;
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len = tp->size - css;
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DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
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DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
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@ -634,8 +637,8 @@ xmit_seg(E1000State *s)
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sofar = frames * tp->mss;
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sofar = frames * tp->mss;
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stl_be_p(tp->data+css+4, ldl_be_p(tp->data+css+4)+sofar); /* seq */
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stl_be_p(tp->data+css+4, ldl_be_p(tp->data+css+4)+sofar); /* seq */
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if (tp->paylen - sofar > tp->mss)
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if (tp->paylen - sofar > tp->mss)
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tp->data[css + 13] &= ~9; // PSH, FIN
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tp->data[css + 13] &= ~9; /* PSH, FIN */
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} else // UDP
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} else /* UDP */
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stw_be_p(tp->data+css+4, len);
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stw_be_p(tp->data+css+4, len);
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if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
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if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
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unsigned int phsum;
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unsigned int phsum;
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@ -657,8 +660,10 @@ xmit_seg(E1000State *s)
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memmove(tp->data, tp->data + 4, 8);
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memmove(tp->data, tp->data + 4, 8);
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memcpy(tp->data + 8, tp->vlan_header, 4);
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memcpy(tp->data + 8, tp->vlan_header, 4);
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e1000_send_packet(s, tp->vlan, tp->size + 4);
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e1000_send_packet(s, tp->vlan, tp->size + 4);
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} else
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} else {
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e1000_send_packet(s, tp->data, tp->size);
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e1000_send_packet(s, tp->data, tp->size);
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}
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s->mac_reg[TPT]++;
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s->mac_reg[TPT]++;
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s->mac_reg[GPTC]++;
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s->mac_reg[GPTC]++;
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n = s->mac_reg[TOTL];
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n = s->mac_reg[TOTL];
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@ -679,7 +684,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
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struct e1000_tx *tp = &s->tx;
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struct e1000_tx *tp = &s->tx;
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s->mit_ide |= (txd_lower & E1000_TXD_CMD_IDE);
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s->mit_ide |= (txd_lower & E1000_TXD_CMD_IDE);
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if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
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if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
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op = le32_to_cpu(xp->cmd_and_length);
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op = le32_to_cpu(xp->cmd_and_length);
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tp->ipcss = xp->lower_setup.ip_fields.ipcss;
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tp->ipcss = xp->lower_setup.ip_fields.ipcss;
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tp->ipcso = xp->lower_setup.ip_fields.ipcso;
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tp->ipcso = xp->lower_setup.ip_fields.ipcso;
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@ -694,7 +699,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
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tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
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tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
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tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
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tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
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tp->tso_frames = 0;
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tp->tso_frames = 0;
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if (tp->tucso == 0) { // this is probably wrong
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if (tp->tucso == 0) { /* this is probably wrong */
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DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
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DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
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tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
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tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
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}
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}
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@ -718,7 +723,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
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stw_be_p(tp->vlan_header + 2,
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stw_be_p(tp->vlan_header + 2,
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le16_to_cpu(dp->upper.fields.special));
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le16_to_cpu(dp->upper.fields.special));
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}
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}
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addr = le64_to_cpu(dp->buffer_addr);
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addr = le64_to_cpu(dp->buffer_addr);
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if (tp->tse && tp->cptse) {
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if (tp->tse && tp->cptse) {
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msh = tp->hdr_len + tp->mss;
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msh = tp->hdr_len + tp->mss;
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@ -1206,41 +1211,46 @@ set_ims(E1000State *s, int index, uint32_t val)
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set_ics(s, 0, 0);
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set_ics(s, 0, 0);
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}
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}
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#define getreg(x) [x] = mac_readreg
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#define getreg(x) [x] = mac_readreg
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static uint32_t (*macreg_readops[])(E1000State *, int) = {
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static uint32_t (*macreg_readops[])(E1000State *, int) = {
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getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
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getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
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getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
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getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
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getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
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getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
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getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
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getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
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getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
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getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
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getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
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getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
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getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
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getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
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getreg(TADV), getreg(ITR),
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getreg(TADV), getreg(ITR),
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[TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
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[TOTH] = mac_read_clr8, [TORH] = mac_read_clr8,
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[GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
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[GPRC] = mac_read_clr4, [GPTC] = mac_read_clr4,
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[ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
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[TPT] = mac_read_clr4, [TPR] = mac_read_clr4,
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[CRCERRS ... MPC] = &mac_readreg,
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[ICR] = mac_icr_read, [EECD] = get_eecd,
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[RA ... RA+31] = &mac_readreg,
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[EERD] = flash_eerd_read,
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[MTA ... MTA+127] = &mac_readreg,
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[CRCERRS ... MPC] = &mac_readreg,
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[RA ... RA+31] = &mac_readreg,
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[MTA ... MTA+127] = &mac_readreg,
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||||||
[VFTA ... VFTA+127] = &mac_readreg,
|
[VFTA ... VFTA+127] = &mac_readreg,
|
||||||
};
|
};
|
||||||
enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
|
enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
|
||||||
|
|
||||||
#define putreg(x) [x] = mac_writereg
|
#define putreg(x) [x] = mac_writereg
|
||||||
static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
|
static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
|
||||||
putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
|
putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
|
||||||
putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
|
putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
|
||||||
putreg(RDBAL), putreg(LEDCTL), putreg(VET),
|
putreg(RDBAL), putreg(LEDCTL), putreg(VET),
|
||||||
[TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
|
|
||||||
[TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
|
[TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
|
||||||
[TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
|
[TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
|
||||||
[IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
|
[TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
|
||||||
[EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
|
[IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
|
||||||
[RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
|
[EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
|
||||||
[ITR] = set_16bit,
|
[RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
|
||||||
[RA ... RA+31] = &mac_writereg,
|
[ITR] = set_16bit,
|
||||||
[MTA ... MTA+127] = &mac_writereg,
|
|
||||||
|
[RA ... RA+31] = &mac_writereg,
|
||||||
|
[MTA ... MTA+127] = &mac_writereg,
|
||||||
[VFTA ... VFTA+127] = &mac_writereg,
|
[VFTA ... VFTA+127] = &mac_writereg,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -158,7 +158,7 @@
|
||||||
#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
|
#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
|
||||||
#define FEXTNVM_SW_CONFIG 0x0001
|
#define FEXTNVM_SW_CONFIG 0x0001
|
||||||
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
|
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
|
||||||
#define E1000_PBS 0x01008 /* Packet Buffer Size */
|
#define E1000_PBS 0x01008 /* Packet Buffer Size - RW */
|
||||||
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
|
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
|
||||||
#define E1000_FLASH_UPDATES 1000
|
#define E1000_FLASH_UPDATES 1000
|
||||||
#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
|
#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
|
||||||
|
|
Loading…
Reference in a new issue