e500: simplify IRQ wiring
The OpenPIC have 5 outputs per connected CPU. The machine init code hence needs a bi-dimensional array (smp_cpu lines, 5 columns) to wire up the irqs between the PIC and the CPUs. The current code first allocates an array of smp_cpus pointers to qemu_irq type, then it allocates another array of smp_cpus * 5 qemu_irq and fills the first array with pointers to each line of the second array. This is rather convoluted. Simplify the logic by introducing a structured type that describes all the OpenPIC outputs for a single CPU, ie, fixed size of 5 qemu_irq, and only allocate a smp_cpu sized array of those. This also allows to use g_new(T, n) instead of g_malloc(sizeof(T) * n) as recommended in HACKING. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -685,7 +685,7 @@ static void ppce500_cpu_reset(void *opaque)
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}
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static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
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qemu_irq **irqs)
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IrqLines *irqs)
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{
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DeviceState *dev;
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SysBusDevice *s;
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@ -705,7 +705,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
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k = 0;
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for (i = 0; i < smp_cpus; i++) {
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for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
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sysbus_connect_irq(s, k++, irqs[i][j]);
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sysbus_connect_irq(s, k++, irqs[i].irq[j]);
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}
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}
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@ -713,7 +713,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
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}
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static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
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qemu_irq **irqs, Error **errp)
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IrqLines *irqs, Error **errp)
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{
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Error *err = NULL;
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DeviceState *dev;
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@ -742,7 +742,7 @@ static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
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static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,
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MemoryRegion *ccsr,
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qemu_irq **irqs)
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IrqLines *irqs)
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{
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MachineState *machine = MACHINE(pms);
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const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
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@ -806,15 +806,14 @@ void ppce500_init(MachineState *machine)
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/* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
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* 4 respectively */
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unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
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qemu_irq **irqs;
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IrqLines *irqs;
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DeviceState *dev, *mpicdev;
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CPUPPCState *firstenv = NULL;
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MemoryRegion *ccsr_addr_space;
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SysBusDevice *s;
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PPCE500CCSRState *ccsr;
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irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
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irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
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irqs = g_new0(IrqLines, smp_cpus);
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for (i = 0; i < smp_cpus; i++) {
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PowerPCCPU *cpu;
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CPUState *cs;
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@ -834,10 +833,9 @@ void ppce500_init(MachineState *machine)
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firstenv = env;
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}
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irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
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input = (qemu_irq *)env->irq_inputs;
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irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
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irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
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irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
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irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
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env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
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env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
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