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target-cris/helper.c: Update Coding Style

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Reindent, add missing braces and drop/adjust whitespace.

Prepares for CPUArchState-to-CPUState field movements in
cpu_cris_handle_mmu_fault(), do_interruptv10() and do_interrupt().
The remaining functions were so minor that they can be fixed in one go.

Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-01-25 17:37:28 +01:00
parent f56e3a1476
commit 21317bc222
1 changed files with 172 additions and 173 deletions
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345
target-cris/helper.c
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@ -36,19 +36,19 @@
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
void do_interrupt (CPUCRISState *env) void do_interrupt(CPUCRISState *env)
{ {
env->exception_index = -1; env->exception_index = -1;
env->pregs[PR_ERP] = env->pc; env->pregs[PR_ERP] = env->pc;
} }
int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw, int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
int mmu_idx) int mmu_idx)
{ {
env->exception_index = 0xaa; env->exception_index = 0xaa;
env->pregs[PR_EDA] = address; env->pregs[PR_EDA] = address;
cpu_dump_state(env, stderr, fprintf, 0); cpu_dump_state(env, stderr, fprintf, 0);
return 1; return 1;
} }
#else /* !CONFIG_USER_ONLY */ #else /* !CONFIG_USER_ONLY */
@ -56,211 +56,210 @@ int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
static void cris_shift_ccs(CPUCRISState *env) static void cris_shift_ccs(CPUCRISState *env)
{ {
uint32_t ccs; uint32_t ccs;
/* Apply the ccs shift. */ /* Apply the ccs shift. */
ccs = env->pregs[PR_CCS]; ccs = env->pregs[PR_CCS];
ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff; ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
env->pregs[PR_CCS] = ccs; env->pregs[PR_CCS] = ccs;
} }
int cpu_cris_handle_mmu_fault (CPUCRISState *env, target_ulong address, int rw, int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
int mmu_idx) int mmu_idx)
{ {
struct cris_mmu_result res; struct cris_mmu_result res;
int prot, miss; int prot, miss;
int r = -1; int r = -1;
target_ulong phy; target_ulong phy;
D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw)); D(printf("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
rw, mmu_idx, 0); rw, mmu_idx, 0);
if (miss) if (miss) {
{ if (env->exception_index == EXCP_BUSFAULT) {
if (env->exception_index == EXCP_BUSFAULT) cpu_abort(env,
cpu_abort(env, "CRIS: Illegal recursive bus fault."
"CRIS: Illegal recursive bus fault." "addr=%x rw=%d\n",
"addr=%x rw=%d\n", address, rw);
address, rw); }
env->pregs[PR_EDA] = address; env->pregs[PR_EDA] = address;
env->exception_index = EXCP_BUSFAULT; env->exception_index = EXCP_BUSFAULT;
env->fault_vector = res.bf_vec; env->fault_vector = res.bf_vec;
r = 1; r = 1;
} } else {
else /*
{ * Mask off the cache selection bit. The ETRAX busses do not
/* * see the top bit.
* Mask off the cache selection bit. The ETRAX busses do not */
* see the top bit. phy = res.phy & ~0x80000000;
*/ prot = res.prot;
phy = res.phy & ~0x80000000; tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
prot = res.prot; prot, mmu_idx, TARGET_PAGE_SIZE);
tlb_set_page(env, address & TARGET_PAGE_MASK, phy, r = 0;
prot, mmu_idx, TARGET_PAGE_SIZE); }
r = 0; if (r > 0) {
} D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
if (r > 0) __func__, r, env->interrupt_request, address, res.phy,
D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n", res.bf_vec, env->pc);
__func__, r, env->interrupt_request, address, res.phy, }
res.bf_vec, env->pc); return r;
return r;
} }
static void do_interruptv10(CPUCRISState *env) static void do_interruptv10(CPUCRISState *env)
{ {
int ex_vec = -1; int ex_vec = -1;
D_LOG( "exception index=%d interrupt_req=%d\n", D_LOG("exception index=%d interrupt_req=%d\n",
env->exception_index, env->exception_index,
env->interrupt_request); env->interrupt_request);
assert(!(env->pregs[PR_CCS] & PFIX_FLAG)); assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
switch (env->exception_index) switch (env->exception_index) {
{ case EXCP_BREAK:
case EXCP_BREAK: /* These exceptions are genereated by the core itself.
/* These exceptions are genereated by the core itself. ERP should point to the insn following the brk. */
ERP should point to the insn following the brk. */ ex_vec = env->trap_vector;
ex_vec = env->trap_vector; env->pregs[PRV10_BRP] = env->pc;
env->pregs[PRV10_BRP] = env->pc; break;
break;
case EXCP_NMI: case EXCP_NMI:
/* NMI is hardwired to vector zero. */ /* NMI is hardwired to vector zero. */
ex_vec = 0; ex_vec = 0;
env->pregs[PR_CCS] &= ~M_FLAG_V10; env->pregs[PR_CCS] &= ~M_FLAG_V10;
env->pregs[PRV10_BRP] = env->pc; env->pregs[PRV10_BRP] = env->pc;
break; break;
case EXCP_BUSFAULT: case EXCP_BUSFAULT:
cpu_abort(env, "Unhandled busfault"); cpu_abort(env, "Unhandled busfault");
break; break;
default: default:
/* The interrupt controller gives us the vector. */ /* The interrupt controller gives us the vector. */
ex_vec = env->interrupt_vector; ex_vec = env->interrupt_vector;
/* Normal interrupts are taken between /* Normal interrupts are taken between
TB's. env->pc is valid here. */ TB's. env->pc is valid here. */
env->pregs[PR_ERP] = env->pc; env->pregs[PR_ERP] = env->pc;
break; break;
} }
if (env->pregs[PR_CCS] & U_FLAG) { if (env->pregs[PR_CCS] & U_FLAG) {
/* Swap stack pointers. */ /* Swap stack pointers. */
env->pregs[PR_USP] = env->regs[R_SP]; env->pregs[PR_USP] = env->regs[R_SP];
env->regs[R_SP] = env->ksp; env->regs[R_SP] = env->ksp;
} }
/* Now that we are in kernel mode, load the handlers address. */ /* Now that we are in kernel mode, load the handlers address. */
env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4); env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
env->locked_irq = 1; env->locked_irq = 1;
env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */ env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
__func__, env->pc, ex_vec, __func__, env->pc, ex_vec,
env->pregs[PR_CCS], env->pregs[PR_CCS],
env->pregs[PR_PID], env->pregs[PR_PID],
env->pregs[PR_ERP]); env->pregs[PR_ERP]);
} }
void do_interrupt(CPUCRISState *env) void do_interrupt(CPUCRISState *env)
{ {
int ex_vec = -1; int ex_vec = -1;
if (env->pregs[PR_VR] < 32) if (env->pregs[PR_VR] < 32) {
return do_interruptv10(env); return do_interruptv10(env);
}
D_LOG( "exception index=%d interrupt_req=%d\n", D_LOG("exception index=%d interrupt_req=%d\n",
env->exception_index, env->exception_index,
env->interrupt_request); env->interrupt_request);
switch (env->exception_index) switch (env->exception_index) {
{ case EXCP_BREAK:
case EXCP_BREAK: /* These exceptions are genereated by the core itself.
/* These exceptions are genereated by the core itself. ERP should point to the insn following the brk. */
ERP should point to the insn following the brk. */ ex_vec = env->trap_vector;
ex_vec = env->trap_vector; env->pregs[PR_ERP] = env->pc;
env->pregs[PR_ERP] = env->pc; break;
break;
case EXCP_NMI: case EXCP_NMI:
/* NMI is hardwired to vector zero. */ /* NMI is hardwired to vector zero. */
ex_vec = 0; ex_vec = 0;
env->pregs[PR_CCS] &= ~M_FLAG_V32; env->pregs[PR_CCS] &= ~M_FLAG_V32;
env->pregs[PR_NRP] = env->pc; env->pregs[PR_NRP] = env->pc;
break; break;
case EXCP_BUSFAULT: case EXCP_BUSFAULT:
ex_vec = env->fault_vector; ex_vec = env->fault_vector;
env->pregs[PR_ERP] = env->pc; env->pregs[PR_ERP] = env->pc;
break; break;
default: default:
/* The interrupt controller gives us the vector. */ /* The interrupt controller gives us the vector. */
ex_vec = env->interrupt_vector; ex_vec = env->interrupt_vector;
/* Normal interrupts are taken between /* Normal interrupts are taken between
TB's. env->pc is valid here. */ TB's. env->pc is valid here. */
env->pregs[PR_ERP] = env->pc; env->pregs[PR_ERP] = env->pc;
break; break;
} }
/* Fill in the IDX field. */ /* Fill in the IDX field. */
env->pregs[PR_EXS] = (ex_vec & 0xff) << 8; env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
if (env->dslot) { if (env->dslot) {
D_LOG("excp isr=%x PC=%x ds=%d SP=%x" D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
" ERP=%x pid=%x ccs=%x cc=%d %x\n", " ERP=%x pid=%x ccs=%x cc=%d %x\n",
ex_vec, env->pc, env->dslot, ex_vec, env->pc, env->dslot,
env->regs[R_SP], env->regs[R_SP],
env->pregs[PR_ERP], env->pregs[PR_PID], env->pregs[PR_ERP], env->pregs[PR_PID],
env->pregs[PR_CCS], env->pregs[PR_CCS],
env->cc_op, env->cc_mask); env->cc_op, env->cc_mask);
/* We loose the btarget, btaken state here so rexec the /* We loose the btarget, btaken state here so rexec the
branch. */ branch. */
env->pregs[PR_ERP] -= env->dslot; env->pregs[PR_ERP] -= env->dslot;
/* Exception starts with dslot cleared. */ /* Exception starts with dslot cleared. */
env->dslot = 0; env->dslot = 0;
} }
if (env->pregs[PR_CCS] & U_FLAG) { if (env->pregs[PR_CCS] & U_FLAG) {
/* Swap stack pointers. */ /* Swap stack pointers. */
env->pregs[PR_USP] = env->regs[R_SP]; env->pregs[PR_USP] = env->regs[R_SP];
env->regs[R_SP] = env->ksp; env->regs[R_SP] = env->ksp;
} }
/* Apply the CRIS CCS shift. Clears U if set. */ /* Apply the CRIS CCS shift. Clears U if set. */
cris_shift_ccs(env); cris_shift_ccs(env);
/* Now that we are in kernel mode, load the handlers address. /* Now that we are in kernel mode, load the handlers address.
This load may not fault, real hw leaves that behaviour as This load may not fault, real hw leaves that behaviour as
undefined. */ undefined. */
env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4); env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
/* Clear the excption_index to avoid spurios hw_aborts for recursive /* Clear the excption_index to avoid spurios hw_aborts for recursive
bus faults. */ bus faults. */
env->exception_index = -1; env->exception_index = -1;
D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
__func__, env->pc, ex_vec, __func__, env->pc, ex_vec,
env->pregs[PR_CCS], env->pregs[PR_CCS],
env->pregs[PR_PID], env->pregs[PR_PID],
env->pregs[PR_ERP]); env->pregs[PR_ERP]);
} }
hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr) hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
{ {
uint32_t phy = addr; uint32_t phy = addr;
struct cris_mmu_result res; struct cris_mmu_result res;
int miss; int miss;
miss = cris_mmu_translate(&res, env, addr, 0, 0, 1); miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
/* If D TLB misses, try I TLB. */ /* If D TLB misses, try I TLB. */
if (miss) { if (miss) {
miss = cris_mmu_translate(&res, env, addr, 2, 0, 1); miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
} }
if (!miss) if (!miss) {
phy = res.phy; phy = res.phy;
D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy)); }
return phy; D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
return phy;
} }
#endif #endif