target/arm: Revise decoding for disas_add_sub_imm
The current Arm ARM has adjusted the official decode of "Add/subtract (immediate)" so that the shift field is only bit 22, and bit 23 is part of the op1 field of the parent category "Data processing - immediate". Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-11-richard.henderson@linaro.org Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3754,22 +3754,22 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
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/*
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* Add/subtract (immediate)
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*
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* 31 30 29 28 24 23 22 21 10 9 5 4 0
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* +--+--+--+-----------+-----+-------------+-----+-----+
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* |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
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* +--+--+--+-----------+-----+-------------+-----+-----+
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* 31 30 29 28 23 22 21 10 9 5 4 0
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* +--+--+--+-------------+--+-------------+-----+-----+
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* |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
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* +--+--+--+-------------+--+-------------+-----+-----+
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*
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* sf: 0 -> 32bit, 1 -> 64bit
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* op: 0 -> add , 1 -> sub
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* S: 1 -> set flags
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* shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
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* sh: 1 -> LSL imm by 12
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*/
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static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
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{
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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uint64_t imm = extract32(insn, 10, 12);
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int shift = extract32(insn, 22, 2);
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bool shift = extract32(insn, 22, 1);
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bool setflags = extract32(insn, 29, 1);
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bool sub_op = extract32(insn, 30, 1);
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bool is_64bit = extract32(insn, 31, 1);
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@ -3778,15 +3778,8 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
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TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd);
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TCGv_i64 tcg_result;
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switch (shift) {
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case 0x0:
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break;
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case 0x1:
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if (shift) {
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imm <<= 12;
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break;
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default:
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unallocated_encoding(s);
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return;
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}
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tcg_result = tcg_temp_new_i64();
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@ -4174,7 +4167,7 @@ static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
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case 0x20: case 0x21: /* PC-rel. addressing */
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disas_pc_rel_adr(s, insn);
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break;
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case 0x22: case 0x23: /* Add/subtract (immediate) */
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case 0x22: /* Add/subtract (immediate) */
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disas_add_sub_imm(s, insn);
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break;
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case 0x24: /* Logical (immediate) */
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