target/ppc: Fix support for "STOP light" states on POWER9
STOP must act differently based on PSSCR:EC on POWER9. When set, it acts like the P7/P8 power management instructions and wake up at 0x100 based on the wakeup conditions in LPCR. When PSSCR:EC is clear however it will wakeup at the next instruction after STOP (if EE is clear) or take the corresponding interrupts (if EE is set). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215161648.9600-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -122,6 +122,7 @@ typedef enum {
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PPC_PM_NAP,
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PPC_PM_SLEEP,
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PPC_PM_RVWINKLE,
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PPC_PM_STOP,
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} powerpc_pm_insn_t;
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/*****************************************************************************/
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@ -414,6 +414,10 @@ struct ppc_slb_t {
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#define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
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#define LPCR_HDICE PPC_BIT(63)
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/* PSSCR bits */
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#define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
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#define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
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#define msr_sf ((env->msr >> MSR_SF) & 1)
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#define msr_isf ((env->msr >> MSR_ISF) & 1)
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#define msr_shv ((env->msr >> MSR_SHV) & 1)
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@ -1110,9 +1114,11 @@ struct CPUPPCState {
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* instructions and SPRs are diallowed if MSR:HV is 0
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*/
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bool has_hv_mode;
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/* On P7/P8, set when in PM state, we need to handle resume
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* in a special way (such as routing some resume causes to
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* 0x100), so flag this here.
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/*
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* On P7/P8/P9, set when in PM state, we need to handle resume in
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* a special way (such as routing some resume causes to 0x100), so
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* flag this here.
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*/
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bool in_pm_state;
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#endif
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@ -97,7 +97,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
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asrr0 = -1;
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asrr1 = -1;
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/* check for special resume at 0x100 from doze/nap/sleep/winkle on P7/P8 */
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/*
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* check for special resume at 0x100 from doze/nap/sleep/winkle on
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* P7/P8/P9
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*/
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if (env->in_pm_state) {
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env->in_pm_state = false;
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@ -960,7 +963,8 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
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env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
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/* Condition for waking up at 0x100 */
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env->in_pm_state = true;
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env->in_pm_state = (insn != PPC_PM_STOP) ||
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(env->spr[SPR_PSSCR] & PSSCR_EC);
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}
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#endif /* defined(TARGET_PPC64) */
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@ -3589,7 +3589,18 @@ static void gen_nap(DisasContext *ctx)
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static void gen_stop(DisasContext *ctx)
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{
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gen_nap(ctx);
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#if defined(CONFIG_USER_ONLY)
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GEN_PRIV;
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#else
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TCGv_i32 t;
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CHK_HV;
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t = tcg_const_i32(PPC_PM_STOP);
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gen_helper_pminsn(cpu_env, t);
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tcg_temp_free_i32(t);
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/* Stop translation, as the CPU is supposed to sleep from now */
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gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
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#endif /* defined(CONFIG_USER_ONLY) */
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}
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static void gen_sleep(DisasContext *ctx)
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@ -8801,9 +8801,16 @@ static bool cpu_has_work_POWER9(CPUState *cs)
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CPUPPCState *env = &cpu->env;
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if (cs->halted) {
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uint64_t psscr = env->spr[SPR_PSSCR];
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if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
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return false;
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}
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/* If EC is clear, just return true on any pending interrupt */
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if (!(psscr & PSSCR_EC)) {
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return true;
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}
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/* External Exception */
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if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
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(env->spr[SPR_LPCR] & LPCR_EEE)) {
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