hw/arm/armsse: Add unimplemented-device stub for cache control registers
The SSE-200 gives each CPU a register bank to use to control its L1 instruction cache. Put in an unimplemented-device stub for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-18-peter.maydell@linaro.org
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@ -32,6 +32,7 @@ struct ARMSSEInfo {
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SysConfigFormat sys_config_format;
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bool has_mhus;
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bool has_ppus;
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bool has_cachectrl;
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};
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static const ARMSSEInfo armsse_variants[] = {
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@ -43,6 +44,7 @@ static const ARMSSEInfo armsse_variants[] = {
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.sys_config_format = IoTKitFormat,
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.has_mhus = false,
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.has_ppus = false,
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.has_cachectrl = false,
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},
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};
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@ -290,6 +292,16 @@ static void armsse_init(Object *obj)
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g_free(name);
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}
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}
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if (info->has_cachectrl) {
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for (i = 0; i < info->num_cpus; i++) {
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char *name = g_strdup_printf("cachectrl%d", i);
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sysbus_init_child_obj(obj, name, &s->cachectrl[i],
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sizeof(s->cachectrl[i]),
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TYPE_UNIMPLEMENTED_DEVICE);
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g_free(name);
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}
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}
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object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate,
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sizeof(s->nmi_orgate), TYPE_OR_IRQ,
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&error_abort, NULL);
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@ -795,7 +807,32 @@ static void armsse_realize(DeviceState *dev, Error **errp)
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qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0,
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armsse_get_common_irq_in(s, 10));
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/* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */
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/*
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* 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias):
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* private per-CPU region (all these devices are SSE-200 only):
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* 0x50010000: L1 icache control registers
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* 0x50011000: CPUSECCTRL (CPU local security control registers)
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* 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
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*/
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if (info->has_cachectrl) {
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for (i = 0; i < info->num_cpus; i++) {
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char *name = g_strdup_printf("cachectrl%d", i);
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MemoryRegion *mr;
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qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name);
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g_free(name);
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qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000);
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object_property_set_bool(OBJECT(&s->cachectrl[i]), true,
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"realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0);
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memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr);
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}
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}
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/* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */
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/* Devices behind APB PPC1:
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@ -150,6 +150,7 @@ typedef struct ARMSSE {
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UnimplementedDeviceState mhu[2];
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UnimplementedDeviceState ppu[NUM_PPUS];
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UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
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/*
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* 'container' holds all devices seen by all CPUs.
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