target/arm: check CF_PARALLEL instead of parallel_cpus
Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -430,8 +430,9 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
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}
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/* Returns 0 on success; 1 otherwise. */
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uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi,
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bool parallel)
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{
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uintptr_t ra = GETPC();
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Int128 oldv, cmpv, newv;
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@ -440,7 +441,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
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cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
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newv = int128_make128(new_lo, new_hi);
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if (parallel_cpus) {
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if (parallel) {
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#ifndef CONFIG_ATOMIC128
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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#else
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@ -484,8 +485,21 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
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return !success;
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}
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uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
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uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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{
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return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false);
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}
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uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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{
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return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true);
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}
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static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi,
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bool parallel)
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{
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uintptr_t ra = GETPC();
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Int128 oldv, cmpv, newv;
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@ -494,7 +508,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
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cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
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newv = int128_make128(new_lo, new_hi);
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if (parallel_cpus) {
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if (parallel) {
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#ifndef CONFIG_ATOMIC128
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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#else
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@ -537,3 +551,15 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
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return !success;
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}
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uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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{
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return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false);
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}
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uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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{
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return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true);
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}
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@ -43,4 +43,8 @@ DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
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DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
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DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
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DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
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DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG,
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i64, env, i64, i64, i64)
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DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
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DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG,
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i64, env, i64, i64, i64)
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@ -502,13 +502,6 @@ void HELPER(yield)(CPUARMState *env)
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ARMCPU *cpu = arm_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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/* When running in MTTCG we don't generate jumps to the yield and
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* WFE helpers as it won't affect the scheduling of other vCPUs.
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* If we wanted to more completely model WFE/SEV so we don't busy
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* spin unnecessarily we would need to do something more involved.
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*/
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g_assert(!parallel_cpus);
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/* This is a non-trappable hint instruction that generally indicates
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* that the guest is currently busy-looping. Yield control back to the
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* top level loop so that a more deserving VCPU has a chance to run.
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@ -1336,13 +1336,18 @@ static void handle_hint(DisasContext *s, uint32_t insn,
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case 3: /* WFI */
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s->base.is_jmp = DISAS_WFI;
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return;
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/* When running in MTTCG we don't generate jumps to the yield and
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* WFE helpers as it won't affect the scheduling of other vCPUs.
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* If we wanted to more completely model WFE/SEV so we don't busy
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* spin unnecessarily we would need to do something more involved.
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*/
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case 1: /* YIELD */
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if (!parallel_cpus) {
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if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
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s->base.is_jmp = DISAS_YIELD;
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}
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return;
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case 2: /* WFE */
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if (!parallel_cpus) {
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if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
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s->base.is_jmp = DISAS_WFE;
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}
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return;
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@ -1931,12 +1936,26 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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MO_64 | MO_ALIGN | s->be_data);
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tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
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} else if (s->be_data == MO_LE) {
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if (tb_cflags(s->base.tb) & CF_PARALLEL) {
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gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env,
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cpu_exclusive_addr,
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cpu_reg(s, rt),
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cpu_reg(s, rt2));
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} else {
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gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr,
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cpu_reg(s, rt), cpu_reg(s, rt2));
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}
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} else {
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if (tb_cflags(s->base.tb) & CF_PARALLEL) {
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gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env,
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cpu_exclusive_addr,
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cpu_reg(s, rt),
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cpu_reg(s, rt2));
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} else {
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gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr,
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cpu_reg(s, rt), cpu_reg(s, rt2));
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}
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}
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} else {
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tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val,
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cpu_reg(s, rt), get_mem_index(s),
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@ -4546,8 +4546,13 @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
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static void gen_nop_hint(DisasContext *s, int val)
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{
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switch (val) {
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/* When running in MTTCG we don't generate jumps to the yield and
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* WFE helpers as it won't affect the scheduling of other vCPUs.
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* If we wanted to more completely model WFE/SEV so we don't busy
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* spin unnecessarily we would need to do something more involved.
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*/
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case 1: /* yield */
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if (!parallel_cpus) {
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if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
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gen_set_pc_im(s, s->pc);
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s->base.is_jmp = DISAS_YIELD;
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}
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@ -4557,7 +4562,7 @@ static void gen_nop_hint(DisasContext *s, int val)
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s->base.is_jmp = DISAS_WFI;
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break;
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case 2: /* wfe */
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if (!parallel_cpus) {
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if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
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gen_set_pc_im(s, s->pc);
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s->base.is_jmp = DISAS_WFE;
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}
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