SYSENTER/SYSEXIT IA-32e implementation (Alexander Graf).
On Intel CPUs, sysenter and sysexit are valid in 64-bit mode. This patch makes both 64-bit aware and enables them for Intel CPUs. Add cpu save/load for 64-bit wide sysenter variables. Signed-off-by: Alexander Graf <agraf@suse.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5318 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -549,8 +549,8 @@ typedef struct CPUX86State {
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/* sysenter registers */
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/* sysenter registers */
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uint32_t sysenter_cs;
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uint32_t sysenter_cs;
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uint32_t sysenter_esp;
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target_ulong sysenter_esp;
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uint32_t sysenter_eip;
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target_ulong sysenter_eip;
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uint64_t efer;
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uint64_t efer;
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uint64_t star;
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uint64_t star;
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@ -737,7 +737,7 @@ static inline int cpu_get_time_fast(void)
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#define cpu_signal_handler cpu_x86_signal_handler
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#define cpu_signal_handler cpu_x86_signal_handler
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#define cpu_list x86_cpu_list
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#define cpu_list x86_cpu_list
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#define CPU_SAVE_VERSION 6
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#define CPU_SAVE_VERSION 7
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/* MMU modes definitions */
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE0_SUFFIX _kernel
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@ -55,7 +55,7 @@ DEF_HELPER(void, helper_enter_level, (int level, int data32, target_ulong t1))
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DEF_HELPER(void, helper_enter64_level, (int level, int data64, target_ulong t1))
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DEF_HELPER(void, helper_enter64_level, (int level, int data64, target_ulong t1))
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#endif
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#endif
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DEF_HELPER(void, helper_sysenter, (void))
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DEF_HELPER(void, helper_sysenter, (void))
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DEF_HELPER(void, helper_sysexit, (void))
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DEF_HELPER(void, helper_sysexit, (int dflag))
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#ifdef TARGET_X86_64
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#ifdef TARGET_X86_64
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DEF_HELPER(void, helper_syscall, (int next_eip_addend))
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DEF_HELPER(void, helper_syscall, (int next_eip_addend))
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DEF_HELPER(void, helper_sysret, (int dflag))
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DEF_HELPER(void, helper_sysret, (int dflag))
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@ -88,9 +88,9 @@ void cpu_save(QEMUFile *f, void *opaque)
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cpu_put_seg(f, &env->gdt);
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cpu_put_seg(f, &env->gdt);
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cpu_put_seg(f, &env->idt);
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cpu_put_seg(f, &env->idt);
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qemu_put_be32s(f, &env->sysenter_cs);
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qemu_put_betls(f, &env->sysenter_cs);
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qemu_put_be32s(f, &env->sysenter_esp);
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qemu_put_betls(f, &env->sysenter_esp);
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qemu_put_be32s(f, &env->sysenter_eip);
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qemu_put_betls(f, &env->sysenter_eip);
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qemu_put_betls(f, &env->cr[0]);
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qemu_put_betls(f, &env->cr[0]);
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qemu_put_betls(f, &env->cr[2]);
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qemu_put_betls(f, &env->cr[2]);
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@ -169,7 +169,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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int32_t a20_mask;
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int32_t a20_mask;
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if (version_id != 3 && version_id != 4 && version_id != 5
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if (version_id != 3 && version_id != 4 && version_id != 5
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&& version_id != 6)
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&& version_id != 6 && version_id != 7)
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return -EINVAL;
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return -EINVAL;
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for(i = 0; i < CPU_NB_REGS; i++)
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for(i = 0; i < CPU_NB_REGS; i++)
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qemu_get_betls(f, &env->regs[i]);
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qemu_get_betls(f, &env->regs[i]);
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@ -244,8 +244,13 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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cpu_get_seg(f, &env->idt);
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cpu_get_seg(f, &env->idt);
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qemu_get_be32s(f, &env->sysenter_cs);
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qemu_get_be32s(f, &env->sysenter_cs);
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if (version_id >= 7) {
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qemu_get_betls(f, &env->sysenter_esp);
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qemu_get_betls(f, &env->sysenter_eip);
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} else {
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qemu_get_be32s(f, &env->sysenter_esp);
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qemu_get_be32s(f, &env->sysenter_esp);
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qemu_get_be32s(f, &env->sysenter_eip);
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qemu_get_be32s(f, &env->sysenter_eip);
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}
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qemu_get_betls(f, &env->cr[0]);
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qemu_get_betls(f, &env->cr[0]);
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qemu_get_betls(f, &env->cr[2]);
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qemu_get_betls(f, &env->cr[2]);
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@ -2919,11 +2919,23 @@ void helper_sysenter(void)
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}
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}
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env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
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env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
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cpu_x86_set_cpl(env, 0);
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cpu_x86_set_cpl(env, 0);
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK |
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DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
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} else
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#endif
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{
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cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
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cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
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0, 0xffffffff,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK |
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DESC_S_MASK |
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DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
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DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
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}
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cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
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cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
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0, 0xffffffff,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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@ -2933,7 +2945,7 @@ void helper_sysenter(void)
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EIP = env->sysenter_eip;
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EIP = env->sysenter_eip;
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}
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}
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void helper_sysexit(void)
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void helper_sysexit(int dflag)
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{
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{
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int cpl;
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int cpl;
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@ -2942,6 +2954,21 @@ void helper_sysexit(void)
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raise_exception_err(EXCP0D_GPF, 0);
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raise_exception_err(EXCP0D_GPF, 0);
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}
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}
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cpu_x86_set_cpl(env, 3);
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cpu_x86_set_cpl(env, 3);
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#ifdef TARGET_X86_64
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if (dflag == 2) {
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cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) | 3,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
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DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
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cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) | 3,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
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DESC_W_MASK | DESC_A_MASK);
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} else
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#endif
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{
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cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3,
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cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3,
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0, 0xffffffff,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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@ -2952,6 +2979,7 @@ void helper_sysexit(void)
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
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DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
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DESC_W_MASK | DESC_A_MASK);
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DESC_W_MASK | DESC_A_MASK);
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}
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ESP = ECX;
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ESP = ECX;
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EIP = EDX;
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EIP = EDX;
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#ifdef USE_KQEMU
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#ifdef USE_KQEMU
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@ -6505,7 +6505,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
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tcg_gen_helper_0_0(helper_rdpmc);
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tcg_gen_helper_0_0(helper_rdpmc);
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break;
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break;
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case 0x134: /* sysenter */
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case 0x134: /* sysenter */
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if (CODE64(s))
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/* For Intel SYSENTER is valid on 64-bit */
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if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
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goto illegal_op;
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goto illegal_op;
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if (!s->pe) {
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if (!s->pe) {
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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@ -6520,7 +6521,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
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}
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}
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break;
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break;
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case 0x135: /* sysexit */
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case 0x135: /* sysexit */
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if (CODE64(s))
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/* For Intel SYSEXIT is valid on 64-bit */
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if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
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goto illegal_op;
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goto illegal_op;
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if (!s->pe) {
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if (!s->pe) {
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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@ -6530,7 +6532,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
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s->cc_op = CC_OP_DYNAMIC;
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s->cc_op = CC_OP_DYNAMIC;
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}
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}
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gen_jmp_im(pc_start - s->cs_base);
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gen_jmp_im(pc_start - s->cs_base);
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tcg_gen_helper_0_0(helper_sysexit);
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tcg_gen_helper_0_1(helper_sysexit, tcg_const_i32(dflag));
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gen_eob(s);
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gen_eob(s);
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}
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}
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break;
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break;
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