sm501: convert to memory API
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
parent
ca3dbc2757
commit
25793bfafa
143
hw/sm501.c
143
hw/sm501.c
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@ -459,7 +459,7 @@ typedef struct SM501State {
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target_phys_addr_t base;
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target_phys_addr_t base;
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uint32_t local_mem_size_index;
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uint32_t local_mem_size_index;
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uint8_t * local_mem;
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uint8_t * local_mem;
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ram_addr_t local_mem_offset;
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MemoryRegion local_mem_region;
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uint32_t last_width;
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uint32_t last_width;
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uint32_t last_height;
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uint32_t last_height;
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@ -726,7 +726,8 @@ static void sm501_2d_operation(SM501State * s)
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}
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}
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}
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}
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static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
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static uint64_t sm501_system_config_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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{
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SM501State * s = (SM501State *)opaque;
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SM501State * s = (SM501State *)opaque;
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uint32_t ret = 0;
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uint32_t ret = 0;
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@ -778,12 +779,12 @@ static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
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return ret;
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return ret;
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}
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}
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static void sm501_system_config_write(void *opaque,
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static void sm501_system_config_write(void *opaque, target_phys_addr_t addr,
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target_phys_addr_t addr, uint32_t value)
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uint64_t value, unsigned size)
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{
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{
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SM501State * s = (SM501State *)opaque;
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SM501State * s = (SM501State *)opaque;
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SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
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SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
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addr, value);
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(uint32_t)addr, (uint32_t)value);
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switch(addr) {
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switch(addr) {
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case SM501_SYSTEM_CONTROL:
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case SM501_SYSTEM_CONTROL:
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@ -821,21 +822,19 @@ static void sm501_system_config_write(void *opaque,
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default:
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default:
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printf("sm501 system config : not implemented register write."
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printf("sm501 system config : not implemented register write."
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" addr=%x, val=%x\n", (int)addr, value);
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" addr=%x, val=%x\n", (int)addr, (uint32_t)value);
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abort();
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abort();
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}
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}
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}
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}
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static CPUReadMemoryFunc * const sm501_system_config_readfn[] = {
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static const MemoryRegionOps sm501_system_config_ops = {
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NULL,
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.read = sm501_system_config_read,
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NULL,
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.write = sm501_system_config_write,
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&sm501_system_config_read,
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.valid = {
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};
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.min_access_size = 4,
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.max_access_size = 4,
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static CPUWriteMemoryFunc * const sm501_system_config_writefn[] = {
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},
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NULL,
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.endianness = DEVICE_NATIVE_ENDIAN,
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NULL,
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&sm501_system_config_write,
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};
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};
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static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
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static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
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@ -864,7 +863,8 @@ static void sm501_palette_write(void *opaque,
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*(uint32_t*)&s->dc_palette[addr] = value;
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*(uint32_t*)&s->dc_palette[addr] = value;
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}
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}
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static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr)
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static uint64_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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{
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SM501State * s = (SM501State *)opaque;
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SM501State * s = (SM501State *)opaque;
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uint32_t ret = 0;
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uint32_t ret = 0;
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@ -958,13 +958,12 @@ static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr)
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return ret;
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return ret;
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}
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}
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static void sm501_disp_ctrl_write(void *opaque,
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static void sm501_disp_ctrl_write(void *opaque, target_phys_addr_t addr,
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target_phys_addr_t addr,
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uint64_t value, unsigned size)
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uint32_t value)
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{
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{
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SM501State * s = (SM501State *)opaque;
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SM501State * s = (SM501State *)opaque;
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SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
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SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
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addr, value);
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(unsigned)addr, (unsigned)value);
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switch(addr) {
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switch(addr) {
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case SM501_DC_PANEL_CONTROL:
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case SM501_DC_PANEL_CONTROL:
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@ -1059,24 +1058,23 @@ static void sm501_disp_ctrl_write(void *opaque,
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default:
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default:
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printf("sm501 disp ctrl : not implemented register write."
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printf("sm501 disp ctrl : not implemented register write."
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" addr=%x, val=%x\n", (int)addr, value);
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" addr=%x, val=%x\n", (int)addr, (unsigned)value);
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abort();
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abort();
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}
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}
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}
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}
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static CPUReadMemoryFunc * const sm501_disp_ctrl_readfn[] = {
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static const MemoryRegionOps sm501_disp_ctrl_ops = {
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NULL,
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.read = sm501_disp_ctrl_read,
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NULL,
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.write = sm501_disp_ctrl_write,
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&sm501_disp_ctrl_read,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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};
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static CPUWriteMemoryFunc * const sm501_disp_ctrl_writefn[] = {
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static uint64_t sm501_2d_engine_read(void *opaque, target_phys_addr_t addr,
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NULL,
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unsigned size)
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NULL,
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&sm501_disp_ctrl_write,
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};
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static uint32_t sm501_2d_engine_read(void *opaque, target_phys_addr_t addr)
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{
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{
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SM501State * s = (SM501State *)opaque;
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SM501State * s = (SM501State *)opaque;
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uint32_t ret = 0;
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uint32_t ret = 0;
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@ -1095,12 +1093,12 @@ static uint32_t sm501_2d_engine_read(void *opaque, target_phys_addr_t addr)
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return ret;
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return ret;
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}
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}
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static void sm501_2d_engine_write(void *opaque,
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static void sm501_2d_engine_write(void *opaque, target_phys_addr_t addr,
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target_phys_addr_t addr, uint32_t value)
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uint64_t value, unsigned size)
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{
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{
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SM501State * s = (SM501State *)opaque;
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SM501State * s = (SM501State *)opaque;
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SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n",
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SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n",
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addr, value);
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(unsigned)addr, (unsigned)value);
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switch(addr) {
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switch(addr) {
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case SM501_2D_SOURCE:
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case SM501_2D_SOURCE:
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@ -1148,21 +1146,19 @@ static void sm501_2d_engine_write(void *opaque,
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break;
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break;
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default:
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default:
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printf("sm501 2d engine : not implemented register write."
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printf("sm501 2d engine : not implemented register write."
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" addr=%x, val=%x\n", (int)addr, value);
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" addr=%x, val=%x\n", (int)addr, (unsigned)value);
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abort();
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abort();
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}
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}
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}
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}
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static CPUReadMemoryFunc * const sm501_2d_engine_readfn[] = {
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static const MemoryRegionOps sm501_2d_engine_ops = {
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NULL,
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.read = sm501_2d_engine_read,
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NULL,
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.write = sm501_2d_engine_write,
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&sm501_2d_engine_read,
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.valid = {
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};
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.min_access_size = 4,
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.max_access_size = 4,
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static CPUWriteMemoryFunc * const sm501_2d_engine_writefn[] = {
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},
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NULL,
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.endianness = DEVICE_NATIVE_ENDIAN,
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NULL,
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&sm501_2d_engine_write,
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};
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};
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/* draw line functions for all console modes */
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/* draw line functions for all console modes */
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@ -1276,7 +1272,7 @@ static void sm501_draw_crt(SM501State * s)
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int y_start = -1;
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int y_start = -1;
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ram_addr_t page_min = ~0l;
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ram_addr_t page_min = ~0l;
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ram_addr_t page_max = 0l;
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ram_addr_t page_max = 0l;
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ram_addr_t offset = s->local_mem_offset;
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ram_addr_t offset = 0;
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/* choose draw_line function */
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/* choose draw_line function */
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switch (s->dc_crt_control & 3) {
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switch (s->dc_crt_control & 3) {
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@ -1333,7 +1329,8 @@ static void sm501_draw_crt(SM501State * s)
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/* check dirty flags for each line */
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/* check dirty flags for each line */
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for (page = page0; page <= page1; page += TARGET_PAGE_SIZE)
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for (page = page0; page <= page1; page += TARGET_PAGE_SIZE)
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if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG))
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if (memory_region_get_dirty(&s->local_mem_region, page,
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DIRTY_MEMORY_VGA))
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update = 1;
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update = 1;
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/* draw line and change status */
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/* draw line and change status */
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@ -1372,8 +1369,9 @@ static void sm501_draw_crt(SM501State * s)
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/* clear dirty flags */
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/* clear dirty flags */
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if (page_min != ~0l) {
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if (page_min != ~0l) {
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cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
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memory_region_reset_dirty(&s->local_mem_region,
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VGA_DIRTY_FLAG);
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page_min, page_max + TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA);
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}
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}
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}
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}
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@ -1390,9 +1388,9 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
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{
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{
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SM501State * s;
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SM501State * s;
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DeviceState *dev;
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DeviceState *dev;
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int sm501_system_config_index;
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MemoryRegion *sm501_system_config = g_new(MemoryRegion, 1);
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int sm501_disp_ctrl_index;
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MemoryRegion *sm501_disp_ctrl = g_new(MemoryRegion, 1);
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int sm501_2d_engine_index;
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MemoryRegion *sm501_2d_engine = g_new(MemoryRegion, 1);
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/* allocate management data region */
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/* allocate management data region */
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s = (SM501State *)g_malloc0(sizeof(SM501State));
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s = (SM501State *)g_malloc0(sizeof(SM501State));
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@ -1407,27 +1405,26 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
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s->dc_crt_control = 0x00010000;
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s->dc_crt_control = 0x00010000;
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/* allocate local memory */
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/* allocate local memory */
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s->local_mem_offset = qemu_ram_alloc(NULL, "sm501.local", local_mem_bytes);
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memory_region_init_ram(&s->local_mem_region, NULL, "sm501.local",
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s->local_mem = qemu_get_ram_ptr(s->local_mem_offset);
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local_mem_bytes);
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cpu_register_physical_memory(base, local_mem_bytes, s->local_mem_offset);
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s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
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memory_region_add_subregion(address_space_mem, base, &s->local_mem_region);
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/* map mmio */
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/* map mmio */
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sm501_system_config_index
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memory_region_init_io(sm501_system_config, &sm501_system_config_ops, s,
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= cpu_register_io_memory(sm501_system_config_readfn,
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"sm501-system-config", 0x6c);
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sm501_system_config_writefn, s,
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memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET,
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DEVICE_NATIVE_ENDIAN);
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sm501_system_config);
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cpu_register_physical_memory(base + MMIO_BASE_OFFSET,
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memory_region_init_io(sm501_disp_ctrl, &sm501_disp_ctrl_ops, s,
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0x6c, sm501_system_config_index);
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"sm501-disp-ctrl", 0x1000);
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sm501_disp_ctrl_index = cpu_register_io_memory(sm501_disp_ctrl_readfn,
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memory_region_add_subregion(address_space_mem,
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sm501_disp_ctrl_writefn, s,
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base + MMIO_BASE_OFFSET + SM501_DC,
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DEVICE_NATIVE_ENDIAN);
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sm501_disp_ctrl);
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cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC,
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memory_region_init_io(sm501_2d_engine, &sm501_2d_engine_ops, s,
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0x1000, sm501_disp_ctrl_index);
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"sm501-2d-engine", 0x54);
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sm501_2d_engine_index = cpu_register_io_memory(sm501_2d_engine_readfn,
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memory_region_add_subregion(address_space_mem,
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sm501_2d_engine_writefn, s,
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base + MMIO_BASE_OFFSET + SM501_2D_ENGINE,
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DEVICE_NATIVE_ENDIAN);
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sm501_2d_engine);
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cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_2D_ENGINE,
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0x54, sm501_2d_engine_index);
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/* bridge to usb host emulation module */
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/* bridge to usb host emulation module */
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dev = qdev_create(NULL, "sysbus-ohci");
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dev = qdev_create(NULL, "sysbus-ohci");
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