target/riscv: Remove decode_RV32_64G()
decodetree handles all instructions now so the fallback is not necessary anymore. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
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@ -651,24 +651,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
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#include "decode_insn16.inc.c"
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#include "insn_trans/trans_rvc.inc.c"
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static void decode_RV32_64G(DisasContext *ctx)
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{
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uint32_t op;
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/* We do not do misaligned address check here: the address should never be
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* misaligned at this point. Instructions that set PC must do the check,
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* since epc must be the address of the instruction that caused us to
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* perform the misaligned instruction fetch */
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op = MASK_OP_MAJOR(ctx->opcode);
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switch (op) {
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default:
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gen_exception_illegal(ctx);
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break;
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}
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}
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static void decode_opc(DisasContext *ctx)
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{
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/* check for compressed insn */
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@ -685,8 +667,7 @@ static void decode_opc(DisasContext *ctx)
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} else {
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ctx->pc_succ_insn = ctx->base.pc_next + 4;
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if (!decode_insn32(ctx, ctx->opcode)) {
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/* fallback to old decoder */
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decode_RV32_64G(ctx);
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gen_exception_illegal(ctx);
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}
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}
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}
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