target-arm queue:
* TLBI ALLEI1IS should operate on all CPUs, not just this one * Fix interval interrupt of cadence ttc in decrement mode * Implement YIELD insn to yield in ARM and Thumb translators * ARM GIC: reset all registers * arm_mptimer: fix timer shutdown and mode change * arm_mptimer: respect IT bit state -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJVmlFDAAoJEDwlJe0UNgze9y8P/1dOW0fITZo9Ld3fIVqJL4lK 9Ihkq9FzCrui0XYoXoP7VBD3qGJE6KdICP1IMvvyEEbgbnMMRa0yXL3pwODRxV0Q 8qNlH4HZyzxYUuT+lHTs7YLgPOOi+UFE/i7ekQBlmdLwBdYvohQAJzjRTMrfLtnv SmB/I+Q5dIp/5FMe2hk1sUZslejMhr/ErDtiFa4w5jEYqHzsPiXlUytVhFIQ7UQI 4OZpQ6SHG65AsnehUp79HPhBSrBpT18j61w3aUYmkn0ENIo1JQdsdoGx09dK6HHF tvQG2sKus0VJmiBJxFN8Rth+pFGyJTeZztTGodU+DlqXl09AykBXMZ6FG4VZLMo5 zw2nK22dBIfMO8suRdYZ6Fk3V4MUoiASrItQp/QuflW2oKHc/gF0/RFX6KkFYdqG UJhQA0Kx/rQzMeNcMwQVZh4jLQtdh9dbRFmY0Lf23BY5+mDfRx1+Z/wSXEc3eSH7 Y7KnjETfkJ21Xf5E+69Aud8yt5puiMywu0/EP03ihl/THMyKiSiVLzRh0sKNTp2j O5neBiypDusqG3dvUYXDWg5y7BO3IoTUtBPkTgKpEe3LaN8g7WkglMmfHeEQeLp2 cXXrhfZ/mbnW4x6Jd+xJIjUEBcS3prr1Exa9p9+9lvV7fJSoS7MVBD4bRWMe5FvX BGktZFm/DGdUSkxL3gne =bBka -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150706' into staging target-arm queue: * TLBI ALLEI1IS should operate on all CPUs, not just this one * Fix interval interrupt of cadence ttc in decrement mode * Implement YIELD insn to yield in ARM and Thumb translators * ARM GIC: reset all registers * arm_mptimer: fix timer shutdown and mode change * arm_mptimer: respect IT bit state # gpg: Signature made Mon Jul 6 10:58:27 2015 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20150706: arm_mptimer: Respect IT bit state arm_mptimer: Fix timer shutdown and mode change hw/intc/arm_gic_common.c: Reset all registers target-arm: Implement YIELD insn to yield in ARM and Thumb translators target-arm: Split DISAS_YIELD from DISAS_WFE Fix interval interrupt of cadence ttc when timer is in decrement mode target-arm: fix write helper for TLBI ALLE1IS Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
261ccf426a
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@ -123,7 +123,7 @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp)
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static void arm_gic_common_reset(DeviceState *dev)
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{
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GICState *s = ARM_GIC_COMMON(dev);
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int i;
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int i, j;
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memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
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for (i = 0 ; i < s->num_cpu; i++) {
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if (s->revision == REV_11MPCORE) {
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@ -135,15 +135,30 @@ static void arm_gic_common_reset(DeviceState *dev)
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s->running_irq[i] = 1023;
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s->running_priority[i] = 0x100;
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s->cpu_ctlr[i] = 0;
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s->bpr[i] = GIC_MIN_BPR;
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s->abpr[i] = GIC_MIN_ABPR;
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for (j = 0; j < GIC_INTERNAL; j++) {
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s->priority1[j][i] = 0;
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}
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for (j = 0; j < GIC_NR_SGIS; j++) {
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s->sgi_pending[j][i] = 0;
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}
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}
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for (i = 0; i < GIC_NR_SGIS; i++) {
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GIC_SET_ENABLED(i, ALL_CPU_MASK);
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GIC_SET_EDGE_TRIGGER(i);
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}
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if (s->num_cpu == 1) {
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for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
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s->priority2[i] = 0;
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}
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for (i = 0; i < GIC_MAXIRQ; i++) {
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/* For uniprocessor GICs all interrupts always target the sole CPU */
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for (i = 0; i < GIC_MAXIRQ; i++) {
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if (s->num_cpu == 1) {
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s->irq_target[i] = 1;
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} else {
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s->irq_target[i] = 0;
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}
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}
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s->ctlr = 0;
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@ -38,7 +38,7 @@ static inline int get_current_cpu(ARMMPTimerState *s)
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static inline void timerblock_update_irq(TimerBlock *tb)
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{
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qemu_set_irq(tb->irq, tb->status);
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qemu_set_irq(tb->irq, tb->status && (tb->control & 4));
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}
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/* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
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@ -122,11 +122,18 @@ static void timerblock_write(void *opaque, hwaddr addr,
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case 8: /* Control. */
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old = tb->control;
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tb->control = value;
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if (((old & 1) == 0) && (value & 1)) {
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if (tb->count == 0 && (tb->control & 2)) {
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if (value & 1) {
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if ((old & 1) && (tb->count != 0)) {
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/* Do nothing if timer is ticking right now. */
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break;
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}
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if (tb->control & 2) {
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tb->count = tb->load;
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}
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timerblock_reload(tb, 1);
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} else if (old & 1) {
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/* Shutdown the timer. */
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timer_del(tb->timer);
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}
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break;
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case 12: /* Interrupt status. */
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@ -208,15 +208,14 @@ static void cadence_timer_sync(CadenceTimerState *s)
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s->reg_intr |= (2 << i);
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}
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}
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if ((x < 0) || (x >= interval)) {
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s->reg_intr |= (s->reg_count & COUNTER_CTRL_INT) ?
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COUNTER_INTR_IV : COUNTER_INTR_OV;
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}
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while (x < 0) {
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x += interval;
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}
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s->reg_value = (uint32_t)(x % interval);
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if (s->reg_value != x) {
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s->reg_intr |= (s->reg_count & COUNTER_CTRL_INT) ?
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COUNTER_INTR_IV : COUNTER_INTR_OV;
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}
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cadence_timer_update(s);
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}
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@ -2441,7 +2441,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbiall_write },
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.writefn = tlbiall_is_write },
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{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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@ -50,6 +50,7 @@ DEF_HELPER_2(exception_internal, void, env, i32)
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DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
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DEF_HELPER_1(wfi, void, env)
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DEF_HELPER_1(wfe, void, env)
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DEF_HELPER_1(yield, void, env)
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DEF_HELPER_1(pre_hvc, void, env)
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DEF_HELPER_2(pre_smc, void, env, i32)
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@ -323,13 +323,25 @@ void HELPER(wfi)(CPUARMState *env)
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void HELPER(wfe)(CPUARMState *env)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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/* Don't actually halt the CPU, just yield back to top
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/* This is a hint instruction that is semantically different
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* from YIELD even though we currently implement it identically.
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* Don't actually halt the CPU, just yield back to top
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* level loop. This is not going into a "low power state"
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* (ie halting until some event occurs), so we never take
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* a configurable trap to a different exception level.
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*/
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HELPER(yield)(env);
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}
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void HELPER(yield)(CPUARMState *env)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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/* This is a non-trappable hint instruction that generally indicates
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* that the guest is currently busy-looping. Yield control back to the
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* top level loop so that a more deserving VCPU has a chance to run.
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*/
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cs->exception_index = EXCP_YIELD;
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cpu_loop_exit(cs);
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}
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@ -1199,6 +1199,8 @@ static void handle_hint(DisasContext *s, uint32_t insn,
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s->is_jmp = DISAS_WFI;
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return;
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case 1: /* YIELD */
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s->is_jmp = DISAS_YIELD;
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return;
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case 2: /* WFE */
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s->is_jmp = DISAS_WFE;
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return;
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@ -11107,6 +11109,10 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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gen_a64_set_pc_im(dc->pc);
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gen_helper_wfe(cpu_env);
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break;
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case DISAS_YIELD:
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gen_a64_set_pc_im(dc->pc);
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gen_helper_yield(cpu_env);
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break;
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case DISAS_WFI:
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/* This is a special case because we don't want to just halt the CPU
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* if trying to debug across a WFI.
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@ -4080,6 +4080,10 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr)
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static void gen_nop_hint(DisasContext *s, int val)
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{
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switch (val) {
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case 1: /* yield */
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gen_set_pc_im(s, s->pc);
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s->is_jmp = DISAS_YIELD;
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break;
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case 3: /* wfi */
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gen_set_pc_im(s, s->pc);
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s->is_jmp = DISAS_WFI;
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@ -11459,6 +11463,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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case DISAS_WFE:
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gen_helper_wfe(cpu_env);
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break;
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case DISAS_YIELD:
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gen_helper_yield(cpu_env);
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break;
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case DISAS_SWI:
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gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
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default_exception_el(dc));
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@ -103,6 +103,7 @@ static inline int default_exception_el(DisasContext *s)
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#define DISAS_WFE 7
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#define DISAS_HVC 8
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#define DISAS_SMC 9
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#define DISAS_YIELD 10
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#ifdef TARGET_AARCH64
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void a64_translate_init(void);
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