haraldwolff/qemu-patch-raspberry4
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

TriCore bugfixes

Browse source 
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCgAGBQJVUKAAAAoJEArSxjlracoU0WgP/Rsuv9C9EL4891vJbQPIyEAu
 Jzho25gx0b9XOnBn6bjTYXf8F5Laiqep7bakOLBp6vctnxY8TyMvwfVJ3vYXr9FD
 SvEJGUjz2ylQ+xxxp3FpeNylLf1Feplvow9sh9/jktf0KeCtUPmXxhEs9C1tUhdC
 75KhYwzAtFp9fhmqyHqgVoCuZweXYt1PbOMx0vIGuLB1BaWwh/+99deIIivZbm95
 WvjDnIhoeaoMdqFNW7yOgSHu8ighY6Jy0x1ui3c5apLAgrMLaYLT2coZGoyGvBD1
 xh722JnTooifSz3HyAXXON4RA+ZSVCNHoSp0Q+pVxEcKPLVCwb4sQJvSZaXJAKur
 mmQAgamDRWKvD9gmxmRQHjE7FrcRp4g3ENkV8KK6i1ZFOU64Qq9GFLPXb7a+XGL0
 6Zt//8as6N98LDl0SUPgxE8U3XIuX14lt2aP6R2wHd8GLVwEmYblehe4KARP/4RY
 vu9gPfCc+JYdI/fHy+GDgkeuurnEQs0a2gIBvAKfvD//ktiFBmLmgxSuo6u5RG/9
 rjXfzuKFUieo5IhqiuSqwwtpJfsxtFy6T4sqzdL4SXMr2R+ycuka3V0JeqlwEJIk
 +hhDoauB5KAAbW5R5CSt5WdEbfrrLRj+aBw8PPiaXqplB53g5pbE6ErhOkgWl0ZY
 q3wiH4umH61dHMcNLSuJ
 =v6rd
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20150511' into staging

TriCore bugfixes

# gpg: Signature made Mon May 11 13:26:40 2015 BST using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>"

* remotes/bkoppelmann/tags/pull-tricore-20150511:
  target-tricore: fix rfe not restoring the PC
  target-tricore: fix rslcx restoring the upper context instead of the lower
  target-tricore: fix BO_OFF10_SEXT calculating the wrong offset
  target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4
  target-tricore: Fix LOOP using wrong register for compare

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2015-05-11 15:07:12 +01:00
parent 9ad2c8cd41 3446a11181
commit 266745cacb
3 changed files with 6 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
target-tricore/op_helper.c
View file

@ -2458,6 +2458,7 @@ void helper_rfe(CPUTriCoreState *env)
if (!cdc_zero(&(env->PSW)) && (env->PSW & MASK_PSW_CDE)) {
/* raise MNG trap */
}
env->PC = env->gpr_a[11] & ~0x1;
/* ICR.IE = PCXI.PIE; */
env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15);
/* ICR.CCPN = PCXI.PCPN; */
@ -2581,7 +2582,7 @@ void helper_rslcx(CPUTriCoreState *env)
((env->PCXI & MASK_PCXI_PCXO) << 6);
/* {new_PCXI, A[11], A[10], A[11], D[8], D[9], D[10], D[11], A[12],
A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
restore_context_upper(env, ea, &new_PCXI, &env->gpr_a[11]);
restore_context_lower(env, ea, &env->gpr_a[11], &new_PCXI);
/* M(EA, word) = FCX; */
cpu_stl_data(env, ea, env->FCX);
/* M(EA, word) = FCX; */

6
target-tricore/translate.c
View file

@ -3440,7 +3440,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
break;
case OPCM_32_BRR_LOOP:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
gen_loop(ctx, r1, offset * 2);
gen_loop(ctx, r2, offset * 2);
} else {
/* OPC2_32_BRR_LOOPU */
gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
@ -3745,10 +3745,10 @@ static void decode_slr_opc(DisasContext *ctx, int op1)
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
break;
case OPC1_16_SLR_LD_W:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
break;
case OPC1_16_SLR_LD_W_POSTINC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
}

2
target-tricore/tricore-opcodes.h
View file

@ -107,7 +107,7 @@
/* BO Format */
#define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \
(MASK_BITS_SHIFT(op, 28, 31) << 6))
#define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT_SEXT(op, 16, 21) + \
#define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT(op, 16, 21) + \
(MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
#define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
#define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15)