target-sh4: define FPSCR constants
Define FPSCR constants for all field and use them instead of hardcoded values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -61,10 +61,37 @@
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#define SR_S (1 << 1)
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#define SR_S (1 << 1)
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#define SR_T (1 << 0)
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#define SR_T (1 << 0)
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#define FPSCR_MASK (0x003fffff)
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#define FPSCR_FR (1 << 21)
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#define FPSCR_FR (1 << 21)
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#define FPSCR_SZ (1 << 20)
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#define FPSCR_SZ (1 << 20)
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#define FPSCR_PR (1 << 19)
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#define FPSCR_PR (1 << 19)
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#define FPSCR_DN (1 << 18)
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#define FPSCR_DN (1 << 18)
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#define FPSCR_CAUSE_MASK (0x3f << 12)
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#define FPSCR_CAUSE_SHIFT (12)
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#define FPSCR_CAUSE_E (1 << 17)
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#define FPSCR_CAUSE_V (1 << 16)
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#define FPSCR_CAUSE_Z (1 << 15)
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#define FPSCR_CAUSE_O (1 << 14)
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#define FPSCR_CAUSE_U (1 << 13)
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#define FPSCR_CAUSE_I (1 << 12)
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#define FPSCR_ENABLE_MASK (0x1f << 7)
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#define FPSCR_ENABLE_SHIFT (7)
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#define FPSCR_ENABLE_V (1 << 11)
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#define FPSCR_ENABLE_Z (1 << 10)
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#define FPSCR_ENABLE_O (1 << 9)
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#define FPSCR_ENABLE_U (1 << 8)
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#define FPSCR_ENABLE_I (1 << 7)
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#define FPSCR_FLAG_MASK (0x1f << 2)
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#define FPSCR_FLAG_SHIFT (2)
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#define FPSCR_FLAG_V (1 << 6)
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#define FPSCR_FLAG_Z (1 << 5)
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#define FPSCR_FLAG_O (1 << 4)
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#define FPSCR_FLAG_U (1 << 3)
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#define FPSCR_FLAG_I (1 << 2)
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#define FPSCR_RM_MASK (0x03 << 0)
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#define FPSCR_RM_NEAREST (0 << 0)
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#define FPSCR_RM_ZERO (1 << 0)
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#define DELAY_SLOT (1 << 0)
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#define DELAY_SLOT (1 << 0)
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#define DELAY_SLOT_CONDITIONAL (1 << 1)
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#define DELAY_SLOT_CONDITIONAL (1 << 1)
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#define DELAY_SLOT_TRUE (1 << 2)
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#define DELAY_SLOT_TRUE (1 << 2)
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@ -443,11 +443,12 @@ static inline void clr_t(void)
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void helper_ld_fpscr(uint32_t val)
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void helper_ld_fpscr(uint32_t val)
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{
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{
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env->fpscr = val & 0x003fffff;
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env->fpscr = val & FPSCR_MASK;
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if (val & 0x01)
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if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
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set_float_rounding_mode(float_round_to_zero, &env->fp_status);
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set_float_rounding_mode(float_round_to_zero, &env->fp_status);
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else
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} else {
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
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}
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}
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}
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uint32_t helper_fabs_FT(uint32_t t0)
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uint32_t helper_fabs_FT(uint32_t t0)
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@ -203,10 +203,10 @@ static void cpu_sh4_reset(CPUSH4State * env)
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env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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#else
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#else
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env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
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env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
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set_float_rounding_mode(float_round_to_zero, &env->fp_status);
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set_float_rounding_mode(float_round_to_zero, &env->fp_status);
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#endif
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#endif
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set_default_nan_mode(1, &env->vfp.fp_status);
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set_default_nan_mode(1, &env->fp_status);
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env->mmucr = 0;
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env->mmucr = 0;
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}
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}
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