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target-arm: Convert cp15 crn=1 registers

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Convert the cp15 crn=1 registers to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2012-06-20 11:57:18 +00:00
parent 34f9052967
commit 2771db2741
3 changed files with 61 additions and 76 deletions
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1
target-arm/cpu-qom.h
View file

@ -97,6 +97,7 @@ typedef struct ARMCPU {
*/
uint32_t ccsidr[16];
uint32_t reset_cbar;
uint32_t reset_auxcr;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)

7
target-arm/cpu.c
View file

@ -77,7 +77,6 @@ static void arm_cpu_reset(CPUState *s)
env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
env->cp15.c0_cachetype = cpu->ctr;
env->cp15.c1_sys = cpu->reset_sctlr;
env->cp15.c0_c1[0] = cpu->id_pfr0;
env->cp15.c0_c1[1] = cpu->id_pfr1;
env->cp15.c0_c1[2] = cpu->id_dfr0;
@ -252,6 +251,7 @@ static void arm1026_initfn(Object *obj)
cpu->reset_fpsid = 0x410110a0;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00090078;
cpu->reset_auxcr = 1;
{
/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
ARMCPRegInfo ifar = {
@ -297,6 +297,7 @@ static void arm1136_r2_initfn(Object *obj)
cpu->id_isar2 = 0x11231111;
cpu->id_isar3 = 0x01102131;
cpu->id_isar4 = 0x141;
cpu->reset_auxcr = 7;
}
static void arm1136_initfn(Object *obj)
@ -326,6 +327,7 @@ static void arm1136_initfn(Object *obj)
cpu->id_isar2 = 0x11231111;
cpu->id_isar3 = 0x01102131;
cpu->id_isar4 = 0x141;
cpu->reset_auxcr = 7;
}
static void arm1176_initfn(Object *obj)
@ -355,6 +357,7 @@ static void arm1176_initfn(Object *obj)
cpu->id_isar2 = 0x11231121;
cpu->id_isar3 = 0x01102131;
cpu->id_isar4 = 0x01141;
cpu->reset_auxcr = 7;
}
static void arm11mpcore_initfn(Object *obj)
@ -381,6 +384,7 @@ static void arm11mpcore_initfn(Object *obj)
cpu->id_isar2 = 0x11221011;
cpu->id_isar3 = 0x01102131;
cpu->id_isar4 = 0x141;
cpu->reset_auxcr = 1;
}
static void cortex_m3_initfn(Object *obj)
@ -430,6 +434,7 @@ static void cortex_a8_initfn(Object *obj)
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
cpu->reset_auxcr = 2;
define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
}

129
target-arm/helper.c
View file

@ -196,6 +196,16 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
REGINFO_SENTINEL
};
static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
if (env->cp15.c1_coproc != value) {
env->cp15.c1_coproc = value;
/* ??? Is this safe when called from within a TB? */
tb_flush(env);
}
return 0;
}
static const ARMCPRegInfo v6_cp_reginfo[] = {
/* prefetch by MVA in v6, NOP in v7 */
{ .name = "MVA_prefetch",
@ -215,6 +225,9 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
*/
{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
{ .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
.resetvalue = 0, .writefn = cpacr_write },
REGINFO_SENTINEL
};
@ -376,6 +389,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
.resetvalue = 0,
.writefn = pmintenclr_write },
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
.resetvalue = 0, },
REGINFO_SENTINEL
};
@ -736,6 +752,10 @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
.cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
.writefn = xscale_cpar_write, },
{ .name = "XSCALE_AUXCR",
.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
.resetvalue = 0, },
REGINFO_SENTINEL
};
@ -785,6 +805,15 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
REGINFO_SENTINEL
};
static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
env->cp15.c1_sys = value;
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(env, 1);
return 0;
}
void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
@ -859,6 +888,31 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_AUXCR)) {
ARMCPRegInfo auxcr = {
.name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST,
.resetvalue = cpu->reset_auxcr
};
define_one_arm_cp_reg(cpu, &auxcr);
}
/* Generic registers whose values depend on the implementation */
{
ARMCPRegInfo sctlr = {
.name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
};
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
/* Normally we would always end the TB on an SCTLR write, but Linux
* arch/arm/mach-pxa/sleep.S expects two instructions following
* an MMU enable to execute from cache. Imitate this behaviour.
*/
sctlr.type |= ARM_CP_SUPPRESS_TB_END;
}
define_one_arm_cp_reg(cpu, &sctlr);
}
}
ARMCPU *cpu_arm_init(const char *cpu_model)
@ -1949,42 +2003,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
break;
}
goto bad_reg;
case 1: /* System configuration. */
if (arm_feature(env, ARM_FEATURE_V7)
&& op1 == 0 && crm == 1 && op2 == 0) {
env->cp15.c1_scr = val;
break;
}
if (arm_feature(env, ARM_FEATURE_OMAPCP))
op2 = 0;
switch (op2) {
case 0:
if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
env->cp15.c1_sys = val;
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(env, 1);
break;
case 1: /* Auxiliary control register. */
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
env->cp15.c1_xscaleauxcr = val;
break;
}
/* Not implemented. */
break;
case 2:
if (arm_feature(env, ARM_FEATURE_XSCALE))
goto bad_reg;
if (env->cp15.c1_coproc != val) {
env->cp15.c1_coproc = val;
/* ??? Is this safe when called from within a TB? */
tb_flush(env);
}
break;
default:
goto bad_reg;
}
break;
case 4: /* Reserved. */
goto bad_reg;
case 12: /* Reserved. */
@ -2085,45 +2103,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
default:
goto bad_reg;
}
case 1: /* System configuration. */
if (arm_feature(env, ARM_FEATURE_V7)
&& op1 == 0 && crm == 1 && op2 == 0) {
return env->cp15.c1_scr;
}
if (arm_feature(env, ARM_FEATURE_OMAPCP))
op2 = 0;
switch (op2) {
case 0: /* Control register. */
return env->cp15.c1_sys;
case 1: /* Auxiliary control register. */
if (arm_feature(env, ARM_FEATURE_XSCALE))
return env->cp15.c1_xscaleauxcr;
if (!arm_feature(env, ARM_FEATURE_AUXCR))
goto bad_reg;
switch (ARM_CPUID(env)) {
case ARM_CPUID_ARM1026:
return 1;
case ARM_CPUID_ARM1136:
case ARM_CPUID_ARM1136_R2:
case ARM_CPUID_ARM1176:
return 7;
case ARM_CPUID_ARM11MPCORE:
return 1;
case ARM_CPUID_CORTEXA8:
return 2;
case ARM_CPUID_CORTEXA9:
case ARM_CPUID_CORTEXA15:
return 0;
default:
goto bad_reg;
}
case 2: /* Coprocessor access register. */
if (arm_feature(env, ARM_FEATURE_XSCALE))
goto bad_reg;
return env->cp15.c1_coproc;
default:
goto bad_reg;
}
case 4: /* Reserved. */
goto bad_reg;
case 11: /* TCM DMA control. */