For upstream
-----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEErET+3BT38evtv0FRKcWWeA9ryoMFAl6qpPUACgkQKcWWeA9r yoOHXAf8D7h7oQjvKTxSdoKHi0KUV3INx816GNdp+ulbUcDZFzjuE9fMOIQ2UmZj qSQ9cdk61zBwZPJMCQ5B8WNlhrXtKEO0lbDkyjwuouyT92vdJ4hNlKFt572RVOAd k3b8FpYTXhPNFC3WSlt/N1QV2KskMKuP+mjpusnhat2Yb3V9Wvm+G1lGS3NBma0B k5/729usRRf+N9EZMsDf1WNIx14gRV8ZaXFX01ztJ91V5TmwrGD/W0Dx6Ch5WqPR 1gnFIaIr5HT7SkbyCQlhep4hcvFJbkAxpCt71lllBoagO3M+fqgOBe0236gsTJ7l bUzMbAjjWqXVo4+IapgPtWq8kAtbAw== =cj39 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2020-04-30.for-upstream' into staging For upstream # gpg: Signature made Thu 30 Apr 2020 11:14:13 BST # gpg: using RSA key AC44FEDC14F7F1EBEDBF415129C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" [unknown] # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" [full] # Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83 * remotes/edgar/tags/edgar/xilinx-next-2020-04-30.for-upstream: target/microblaze: Add the pvr-user2 property target/microblaze: Add the pvr-user1 property target/microblaze: Add the unaligned-exceptions property target/microblaze: Add the div-zero-exception property target/microblaze: Add the ill-opcode-exception property target/microblaze: Add the opcode-0x0-illegal CPU property Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
27c9456637
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@ -193,8 +193,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
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(cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
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(version_code << PVR0_VERSION_SHIFT) |
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(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
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(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
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cpu->cfg.pvr_user1;
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env->pvr.regs[1] = cpu->cfg.pvr_user2;
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env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
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(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
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(cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
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@ -206,7 +208,15 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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(cpu->cfg.dopb_bus_exception ?
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PVR2_DOPB_BUS_EXC_MASK : 0) |
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(cpu->cfg.iopb_bus_exception ?
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PVR2_IOPB_BUS_EXC_MASK : 0);
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PVR2_IOPB_BUS_EXC_MASK : 0) |
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(cpu->cfg.div_zero_exception ?
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PVR2_DIV_ZERO_EXC_MASK : 0) |
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(cpu->cfg.illegal_opcode_exception ?
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PVR2_ILL_OPCODE_EXC_MASK : 0) |
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(cpu->cfg.unaligned_exceptions ?
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PVR2_UNALIGNED_EXC_MASK : 0) |
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(cpu->cfg.opcode_0_illegal ?
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PVR2_OPCODE_0x0_ILL_MASK : 0);
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env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
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PVR5_DCACHE_WRITEBACK_MASK : 0;
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@ -274,8 +284,18 @@ static Property mb_properties[] = {
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/* Enables bus exceptions on failed instruction fetches. */
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DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
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cfg.iopb_bus_exception, false),
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DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
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cfg.illegal_opcode_exception, false),
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DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
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cfg.div_zero_exception, false),
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DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
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cfg.unaligned_exceptions, false),
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DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
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cfg.opcode_0_illegal, false),
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DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
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DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
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DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
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DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -303,6 +303,12 @@ struct MicroBlazeCPU {
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bool endi;
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bool dopb_bus_exception;
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bool iopb_bus_exception;
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bool illegal_opcode_exception;
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bool opcode_0_illegal;
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bool div_zero_exception;
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bool unaligned_exceptions;
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uint8_t pvr_user1;
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uint32_t pvr_user2;
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char *version;
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uint8_t pvr;
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} cfg;
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@ -132,11 +132,12 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
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static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
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{
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MicroBlazeCPU *cpu = env_archcpu(env);
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if (b == 0) {
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env->sregs[SR_MSR] |= MSR_DZ;
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if ((env->sregs[SR_MSR] & MSR_EE)
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&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
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if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) {
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env->sregs[SR_ESR] = ESR_EC_DIVZERO;
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helper_raise_exception(env, EXCP_HW_EXCP);
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}
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@ -185,7 +185,7 @@ static void write_carryi(DisasContext *dc, bool carry)
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static bool trap_illegal(DisasContext *dc, bool cond)
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{
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if (cond && (dc->tb_flags & MSR_EE_FLAG)
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&& (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
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&& dc->cpu->cfg.illegal_opcode_exception) {
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tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
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t_gen_raise_exception(dc, EXCP_HW_EXCP);
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}
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@ -995,7 +995,7 @@ static void dec_load(DisasContext *dc)
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v = tcg_temp_new_i32();
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tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
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if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
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TCGv_i32 t0 = tcg_const_i32(0);
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TCGv_i32 treg = tcg_const_i32(dc->rd);
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TCGv_i32 tsize = tcg_const_i32(size - 1);
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@ -1110,7 +1110,7 @@ static void dec_store(DisasContext *dc)
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tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
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/* Verify alignment if needed. */
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if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
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TCGv_i32 t1 = tcg_const_i32(1);
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TCGv_i32 treg = tcg_const_i32(dc->rd);
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TCGv_i32 tsize = tcg_const_i32(size - 1);
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@ -1573,7 +1573,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
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LOG_DIS("%8.8x\t", dc->ir);
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if (ir == 0) {
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trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK);
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trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal);
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/* Don't decode nop/zero instructions any further. */
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return;
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}
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