target-mips: remove misleading comments in translate_init.c
PABITS are not hardcoded to 36 bits and we do not model 59 PABITS (which is the architectural limit) in QEMU. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -553,9 +553,6 @@ static const mips_def_t mips_defs[] =
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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.SEGBITS = 42,
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.SEGBITS = 42,
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/* The architectural limit is 59, but we have hardcoded 36 bit
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in some places...
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.PABITS = 59, */ /* the architectural limit */
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.PABITS = 36,
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.PABITS = 36,
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.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
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.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
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.mmu_type = MMU_TYPE_R4000,
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.mmu_type = MMU_TYPE_R4000,
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@ -637,9 +634,6 @@ static const mips_def_t mips_defs[] =
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(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
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(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
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(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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.SEGBITS = 42,
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.SEGBITS = 42,
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/* The architectural limit is 59, but we have hardcoded 36 bit
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in some places...
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.PABITS = 59, */ /* the architectural limit */
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.PABITS = 36,
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.PABITS = 36,
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.insn_flags = CPU_MIPS64R6,
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.insn_flags = CPU_MIPS64R6,
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.mmu_type = MMU_TYPE_R4000,
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.mmu_type = MMU_TYPE_R4000,
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@ -703,9 +697,6 @@ static const mips_def_t mips_defs[] =
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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.SEGBITS = 42,
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.SEGBITS = 42,
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/* The architectural limit is 59, but we have hardcoded 36 bit
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in some places...
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.PABITS = 59, */ /* the architectural limit */
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.PABITS = 36,
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.PABITS = 36,
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.insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
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.insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
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.mmu_type = MMU_TYPE_R4000,
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.mmu_type = MMU_TYPE_R4000,
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