Fixes for 3 tcg bugs
-----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAl0rDcUdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+lhwf5AXr70c2OT2lXG+Jo EzGhNTfEp5+NHW5Pq9YzyS9XgI2JarvsdANiK+BQPG3m1vgKmbU5wyluMPEdJ734 pmZT6uie9z4t0U2xTwwJvw5zrDNcZB07pTg4X4AdSUn3UnqLGVR1yuk1Tisf8fBD 46O5JDJQkXjctWEJYyqPU0wCiOTrDiwmI+EJjvOAupabAcYLJSFrg6cv7a/oUTjY D4lckL2Hc0RyAFRnCnxcXVd+ivYkVdyVyzz0p8oGlWeQvmHZ8K77vJJ3YD1jz8S0 6c/MJMyCsTEzV68D7UZijFWACCPI/htoScTFqChwtdckSy9N0qWrKtSUQd+eIsV1 UkGv6g== =zmEG -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190714' into staging Fixes for 3 tcg bugs # gpg: Signature made Sun 14 Jul 2019 12:11:01 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190714: tcg: Release mmap_lock on translation fault tcg: Remove duplicate #if !defined(CODE_ACCESS) tcg: Remove cpu_ld*_code_ra tcg: Introduce set/clear_helper_retaddr include/qemu/atomic.h: Add signal_barrier tcg/aarch64: Fix output of extract2 opcodes tcg: Fix constant folding of INDEX_op_extract2_i32 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
298ad7b5a4
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@ -64,27 +64,56 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
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CPUState *cpu = current_cpu;
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CPUClass *cc;
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unsigned long address = (unsigned long)info->si_addr;
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MMUAccessType access_type;
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MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
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/* We must handle PC addresses from two different sources:
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* a call return address and a signal frame address.
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*
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* Within cpu_restore_state_from_tb we assume the former and adjust
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* the address by -GETPC_ADJ so that the address is within the call
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* insn so that addr does not accidentally match the beginning of the
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* next guest insn.
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*
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* However, when the PC comes from the signal frame, it points to
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* the actual faulting host insn and not a call insn. Subtracting
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* GETPC_ADJ in that case may accidentally match the previous guest insn.
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*
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* So for the later case, adjust forward to compensate for what
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* will be done later by cpu_restore_state_from_tb.
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*/
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if (helper_retaddr) {
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switch (helper_retaddr) {
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default:
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/*
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* Fault during host memory operation within a helper function.
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* The helper's host return address, saved here, gives us a
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* pointer into the generated code that will unwind to the
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* correct guest pc.
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*/
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pc = helper_retaddr;
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} else {
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break;
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case 0:
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/*
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* Fault during host memory operation within generated code.
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* (Or, a unrelated bug within qemu, but we can't tell from here).
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*
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* We take the host pc from the signal frame. However, we cannot
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* use that value directly. Within cpu_restore_state_from_tb, we
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* assume PC comes from GETPC(), as used by the helper functions,
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* so we adjust the address by -GETPC_ADJ to form an address that
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* is within the call insn, so that the address does not accidentially
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* match the beginning of the next guest insn. However, when the
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* pc comes from the signal frame it points to the actual faulting
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* host memory insn and not the return from a call insn.
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*
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* Therefore, adjust to compensate for what will be done later
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* by cpu_restore_state_from_tb.
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*/
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pc += GETPC_ADJ;
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break;
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case 1:
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/*
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* Fault during host read for translation, or loosely, "execution".
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*
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* The guest pc is already pointing to the start of the TB for which
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* code is being generated. If the guest translator manages the
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* page crossings correctly, this is exactly the correct address
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* (and if the translator doesn't handle page boundaries correctly
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* there's little we can do about that here). Therefore, do not
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* trigger the unwinder.
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*
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* Like tb_gen_code, release the memory lock before cpu_loop_exit.
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*/
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pc = 0;
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access_type = MMU_INST_FETCH;
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mmap_unlock();
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break;
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}
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/* For synchronous signals we expect to be coming from the vCPU
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@ -134,7 +163,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
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* currently executing TB was modified and must be exited
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* immediately. Clear helper_retaddr for next execution.
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*/
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helper_retaddr = 0;
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clear_helper_retaddr();
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cpu_exit_tb_from_sighandler(cpu, old_set);
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/* NORETURN */
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@ -152,10 +181,9 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
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* an exception. Undo signal and retaddr state prior to longjmp.
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*/
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sigprocmask(SIG_SETMASK, old_set, NULL);
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helper_retaddr = 0;
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clear_helper_retaddr();
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cc = CPU_GET_CLASS(cpu);
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access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
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cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
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g_assert_not_reached();
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}
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@ -682,14 +710,15 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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if (unlikely(addr & (size - 1))) {
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cpu_loop_exit_atomic(env_cpu(env), retaddr);
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}
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helper_retaddr = retaddr;
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return g2h(addr);
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void *ret = g2h(addr);
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set_helper_retaddr(retaddr);
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return ret;
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}
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/* Macro to call the above, with local variables from the use context. */
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#define ATOMIC_MMU_DECLS do {} while (0)
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#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC())
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#define ATOMIC_MMU_CLEANUP do { helper_retaddr = 0; } while (0)
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#define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0)
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#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
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#define EXTRA_ARGS
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@ -89,6 +89,26 @@ typedef target_ulong abi_ptr;
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extern __thread uintptr_t helper_retaddr;
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static inline void set_helper_retaddr(uintptr_t ra)
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{
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helper_retaddr = ra;
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/*
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* Ensure that this write is visible to the SIGSEGV handler that
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* may be invoked due to a subsequent invalid memory operation.
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*/
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signal_barrier();
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}
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static inline void clear_helper_retaddr(void)
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{
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/*
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* Ensure that previous memory operations have succeeded before
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* removing the data visible to the signal handler.
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*/
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signal_barrier();
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helper_retaddr = 0;
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}
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/* In user-only mode we provide only the _code and _data accessors. */
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#define MEMSUFFIX _data
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@ -64,61 +64,75 @@
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static inline RES_TYPE
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glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr)
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{
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#if !defined(CODE_ACCESS)
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#ifdef CODE_ACCESS
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RES_TYPE ret;
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set_helper_retaddr(1);
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ret = glue(glue(ld, USUFFIX), _p)(g2h(ptr));
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clear_helper_retaddr();
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return ret;
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#else
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trace_guest_mem_before_exec(
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env_cpu(env), ptr,
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trace_mem_build_info(SHIFT, false, MO_TE, false));
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#endif
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return glue(glue(ld, USUFFIX), _p)(g2h(ptr));
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#endif
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}
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#ifndef CODE_ACCESS
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static inline RES_TYPE
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glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
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abi_ptr ptr,
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uintptr_t retaddr)
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{
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RES_TYPE ret;
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helper_retaddr = retaddr;
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set_helper_retaddr(retaddr);
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ret = glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(env, ptr);
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helper_retaddr = 0;
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clear_helper_retaddr();
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return ret;
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}
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#endif
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#if DATA_SIZE <= 2
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static inline int
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glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr)
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{
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#if !defined(CODE_ACCESS)
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#ifdef CODE_ACCESS
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int ret;
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set_helper_retaddr(1);
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ret = glue(glue(lds, SUFFIX), _p)(g2h(ptr));
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clear_helper_retaddr();
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return ret;
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#else
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trace_guest_mem_before_exec(
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env_cpu(env), ptr,
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trace_mem_build_info(SHIFT, true, MO_TE, false));
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#endif
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return glue(glue(lds, SUFFIX), _p)(g2h(ptr));
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#endif
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}
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#ifndef CODE_ACCESS
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static inline int
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glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
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abi_ptr ptr,
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uintptr_t retaddr)
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{
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int ret;
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helper_retaddr = retaddr;
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set_helper_retaddr(retaddr);
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ret = glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(env, ptr);
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helper_retaddr = 0;
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clear_helper_retaddr();
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return ret;
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}
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#endif
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#endif /* CODE_ACCESS */
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#endif /* DATA_SIZE <= 2 */
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#ifndef CODE_ACCESS
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static inline void
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glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr,
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RES_TYPE v)
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{
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#if !defined(CODE_ACCESS)
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trace_guest_mem_before_exec(
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env_cpu(env), ptr,
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trace_mem_build_info(SHIFT, false, MO_TE, true));
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#endif
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glue(glue(st, SUFFIX), _p)(g2h(ptr), v);
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}
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@ -128,9 +142,9 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
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RES_TYPE v,
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uintptr_t retaddr)
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{
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helper_retaddr = retaddr;
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set_helper_retaddr(retaddr);
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glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(env, ptr, v);
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helper_retaddr = 0;
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clear_helper_retaddr();
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}
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#endif
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@ -88,6 +88,13 @@
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#define smp_read_barrier_depends() barrier()
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#endif
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/*
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* A signal barrier forces all pending local memory ops to be observed before
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* a SIGSEGV is delivered to the *same* thread. In practice this is exactly
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* the same as barrier(), but since we have the correct builtin, use it.
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*/
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#define signal_barrier() __atomic_signal_fence(__ATOMIC_SEQ_CST)
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/* Sanity check that the size of an atomic operation isn't "overly large".
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* Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
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* want to use them because we ought not need them, and this lets us do a
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@ -308,6 +315,10 @@
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#define smp_read_barrier_depends() barrier()
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#endif
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#ifndef signal_barrier
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#define signal_barrier() barrier()
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#endif
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/* These will only be atomic if the processor does the fetch or store
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* in a single issue memory operation
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*/
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@ -554,7 +554,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
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/* ??? Enforce alignment. */
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uint64_t *haddr = g2h(addr);
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helper_retaddr = ra;
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set_helper_retaddr(ra);
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o0 = ldq_le_p(haddr + 0);
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o1 = ldq_le_p(haddr + 1);
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oldv = int128_make128(o0, o1);
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@ -564,7 +564,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
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stq_le_p(haddr + 0, int128_getlo(newv));
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stq_le_p(haddr + 1, int128_gethi(newv));
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}
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helper_retaddr = 0;
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clear_helper_retaddr();
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
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@ -624,7 +624,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
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/* ??? Enforce alignment. */
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uint64_t *haddr = g2h(addr);
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helper_retaddr = ra;
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set_helper_retaddr(ra);
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o1 = ldq_be_p(haddr + 0);
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o0 = ldq_be_p(haddr + 1);
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oldv = int128_make128(o0, o1);
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@ -634,7 +634,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
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stq_be_p(haddr + 0, int128_gethi(newv));
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stq_be_p(haddr + 1, int128_getlo(newv));
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}
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helper_retaddr = 0;
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clear_helper_retaddr();
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
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@ -4125,12 +4125,11 @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
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return MIN(split, mem_max - mem_off) + mem_off;
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}
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static inline void set_helper_retaddr(uintptr_t ra)
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{
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#ifdef CONFIG_USER_ONLY
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helper_retaddr = ra;
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#ifndef CONFIG_USER_ONLY
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/* These are normally defined only for CONFIG_USER_ONLY in <exec/cpu_ldst.h> */
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static inline void set_helper_retaddr(uintptr_t ra) { }
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static inline void clear_helper_retaddr(void) { }
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#endif
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}
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/*
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* The result of tlb_vaddr_to_host for user-only is just g2h(x),
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|
@ -4188,7 +4187,7 @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
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if (test_host_page(host)) {
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mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
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tcg_debug_assert(mem_off == mem_max);
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set_helper_retaddr(0);
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clear_helper_retaddr();
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/* After having taken any fault, zero leading inactive elements. */
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swap_memzero(vd, reg_off);
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return;
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|
@ -4239,7 +4238,7 @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
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}
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#endif
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set_helper_retaddr(0);
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clear_helper_retaddr();
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memcpy(vd, &scratch, reg_max);
|
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}
|
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|
@ -4312,7 +4311,7 @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
|
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addr += 2 * size;
|
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} while (i & 15);
|
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}
|
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set_helper_retaddr(0);
|
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clear_helper_retaddr();
|
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|
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/* Wait until all exceptions have been raised to write back. */
|
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memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
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|
@ -4341,7 +4340,7 @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
|
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addr += 3 * size;
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} while (i & 15);
|
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}
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set_helper_retaddr(0);
|
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clear_helper_retaddr();
|
||||
|
||||
/* Wait until all exceptions have been raised to write back. */
|
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memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
|
||||
|
@ -4372,7 +4371,7 @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
|
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addr += 4 * size;
|
||||
} while (i & 15);
|
||||
}
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
|
||||
/* Wait until all exceptions have been raised to write back. */
|
||||
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
|
||||
|
@ -4494,7 +4493,7 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
|
|||
if (test_host_page(host)) {
|
||||
mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
|
||||
tcg_debug_assert(mem_off == mem_max);
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
/* After any fault, zero any leading inactive elements. */
|
||||
swap_memzero(vd, reg_off);
|
||||
return;
|
||||
|
@ -4537,7 +4536,7 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
|
|||
}
|
||||
#endif
|
||||
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
record_fault(env, reg_off, reg_max);
|
||||
}
|
||||
|
||||
|
@ -4740,7 +4739,7 @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
|
|||
addr += msize;
|
||||
} while (i & 15);
|
||||
}
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
|
||||
|
@ -4766,7 +4765,7 @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
|
|||
addr += 2 * msize;
|
||||
} while (i & 15);
|
||||
}
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
|
||||
|
@ -4794,7 +4793,7 @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
|
|||
addr += 3 * msize;
|
||||
} while (i & 15);
|
||||
}
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
|
||||
|
@ -4824,7 +4823,7 @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
|
|||
addr += 4 * msize;
|
||||
} while (i & 15);
|
||||
}
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
#define DO_STN_1(N, NAME, ESIZE) \
|
||||
|
@ -4932,7 +4931,7 @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
|
|||
i += 4, pg >>= 4;
|
||||
} while (i & 15);
|
||||
}
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
|
||||
/* Wait until all exceptions have been raised to write back. */
|
||||
memcpy(vd, &scratch, oprsz);
|
||||
|
@ -4955,7 +4954,7 @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
|
|||
tlb_fn(env, &scratch, i * 8, base + (off << scale), oi, ra);
|
||||
}
|
||||
}
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
|
||||
/* Wait until all exceptions have been raised to write back. */
|
||||
memcpy(vd, &scratch, oprsz * 8);
|
||||
|
@ -5133,7 +5132,7 @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
|
|||
tlb_fn(env, vd, reg_off, addr, oi, ra);
|
||||
|
||||
/* The rest of the reads will be non-faulting. */
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
/* After any fault, zero the leading predicated false elements. */
|
||||
|
@ -5175,7 +5174,7 @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
|
|||
tlb_fn(env, vd, reg_off, addr, oi, ra);
|
||||
|
||||
/* The rest of the reads will be non-faulting. */
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
/* After any fault, zero the leading predicated false elements. */
|
||||
|
@ -5299,7 +5298,7 @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
|
|||
i += 4, pg >>= 4;
|
||||
} while (i & 15);
|
||||
}
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
|
||||
|
@ -5318,7 +5317,7 @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
|
|||
tlb_fn(env, vd, i * 8, base + (off << scale), oi, ra);
|
||||
}
|
||||
}
|
||||
set_helper_retaddr(0);
|
||||
clear_helper_retaddr();
|
||||
}
|
||||
|
||||
#define DO_ST1_ZPZ_S(MEM, OFS) \
|
||||
|
|
|
@ -2226,7 +2226,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
|||
|
||||
case INDEX_op_extract2_i64:
|
||||
case INDEX_op_extract2_i32:
|
||||
tcg_out_extr(s, ext, a0, a1, a2, args[3]);
|
||||
tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]);
|
||||
break;
|
||||
|
||||
case INDEX_op_add2_i32:
|
||||
|
|
|
@ -1213,8 +1213,8 @@ void tcg_optimize(TCGContext *s)
|
|||
if (opc == INDEX_op_extract2_i64) {
|
||||
tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3]));
|
||||
} else {
|
||||
tmp = (v1 >> op->args[3]) | (v2 << (32 - op->args[3]));
|
||||
tmp = (int32_t)tmp;
|
||||
tmp = (int32_t)(((uint32_t)v1 >> op->args[3]) |
|
||||
((uint32_t)v2 << (32 - op->args[3])));
|
||||
}
|
||||
tcg_opt_gen_movi(s, op, op->args[0], tmp);
|
||||
break;
|
||||
|
|
Loading…
Reference in a new issue